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AD4134 Datasheet(PDF) 74 Page - Analog Devices |
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AD4134 Datasheet(HTML) 74 Page - Analog Devices |
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74 / 92 page  Data Sheet AD4134 REGISTER MAP (SPI CONTROL) analog.com Rev. 0 | 74 of 92 See Table 38 for the register map for the device (SPI control). Table 38. Register Map Reg Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW 0x0 INTERFACE_ CONFIG_A SOFT_ RESET Reserved ADDRESS_ ASCENSION_ BIT SDO_ ACTIVE_ BIT SDO_ ACTIVE_ BIT_ MIRROR ADDRESS_ ASCENSION_ BIT_MIRROR Reserved SOFT_ RESET_ MIRROR 0x18 R/W 0x1 INTERFACE_ CONFIG_B SINGLE_ INSTR Reserved MASTER_ SLAVE_ RD_CTRL Reserved DIG_IF_ RESET Reserved 0x80 R/W 0x2 DEVICE_CONFIG Reserved OP_IN_ PROGRESS NO_CHIP_ ERR Reserved POWER_ MODE 0xD0 R/W 0x3 CHIP_TYPE CHIP_TYPE 0x07 R 0x4 PRODUCT_ID_LSB PRODUCT_ID[7:0] N/A1 R 0x5 PRODUCT_ID_MSB PRODUCT_ID[15:8] N/A1 R 0x6 CHIP_GRADE PRODUCT_GRADE DEVICE_VERSION 0x00 R 0x7 SILICON_REV SILICON_REVISION_ID 0x00 R 0xA SCRATCH_PAD SCRATCH_PAD 0x00 R/W 0xB SPI_REVISION SPI_REVSION_NUMBER 0x02 R 0xC VENDOR_ID_LSB VENDOR_ID[7:0] 0x56 R 0xD VENDOR_ID_MSB VENDOR_ID[15:8] 0x04 R 0xE STREAM_MODE STREAM_MODE_BITS 0x00 R/W 0xF TRANSFER_ REGISTER Reserved MASTER_ SLAVE_ TX_BIT 0x00 R/W 0x10 DEVICE_CONFIG_1 Reserved AA_MODE SDO_PIN_ SRC_SEL REFIN_ GAIN_ CORR_EN XCLKOUT_ EN 0x00 R/W 0x11 DATA_PACKET_ CONFIG CRC_ POLY_ RST_ SEL Reserved Frame DCLK_FREQ_SEL 0x00 R/W 0x12 DIGITAL_INTERFACE _ CONFIG DAISY_CHAIN_DEV_NUM AVG_SEL Format 0x00 R/W 0x13 POWER_DOWN_ CONTROL Reserved PWRDN_ CH3 PWRDN_ CH2 PWRDN_ CH1 PWRDN_ CH0 Reserved PWRDN_ LDO SLEEP_ MODE_EN 0x00 R/W 0x14 RESERVED Reserved 0x00 R/W 0x15 DEVICE_STATUS Reserved STAT_ DCLKMODE STAT_ DCLKIO STAT_ MODE STAT_ CLKSEL STAT_ FUSE_ ECC STAT_PLL_ LOCK 0x00 R 0x16 ODR_VAL_INT_LSB ODR_VAL_INT[7:0] 0x40 R/W 0x17 ODR_VAL_INT_MID ODR_VAL_INT[15:8] 0x00 R/W 0x18 ODR_VAL_INT_MSB ODR_VAL_INT[23:16] 0x00 R/W 0x19 ODR_VAL_FLT_LSB ODR_VAL_FLT[7:0] 0x72 R/W 0x1A ODR_VAL_FLT_MID0 ODR_VAL_FLT[15:8] 0xB7 R/W 0x1B ODR_VAL_FLT_MID1 ODR_VAL_FLT[23:16] 0xCE R/W 0x1C ODR_VAL_FLT_MSB ODR_VAL_FLT[31:24] 0x2B R/W 0x1D CHANNEL_ODR_ SELECT ODR_RATE_SEL_CH3 ODR_RATE_SEL_CH2 ODR_RATE_SEL_CH1 ODR_RATE_SEL_CH0 0x00 R/W 0x1E CHAN_DIG_ FILTER_SEL DIGFILTER_SEL_CH3 DIGFILTER_SEL_CH2 DIGFILTER_SEL_CH1 DIGFILTER_SEL_CH0 0x00 R/W |
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