AD4134 datasheet(86/92 Pages) AD

86 / 92 page

Data Sheet

AD4134

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Rev. 0 | 86 of 92

Table 73. Bit Descriptions for VCMBUF_CTRL

Bits

Bit Name

Settings

Description

Reset

Access

10011 VCM = VREF × 1/20.

11101 VCM = VREF × 10/20.

11110 VCM = VREF × 10/20.

11111 VCM = VREF × 10/20.

VCMBUF_REF_SEL

VCM Output Source Selection.

0x0

R/W

0 VCM as a ratio of VREF. The VCM output level is VREF divided by the ratio set with

VCMBUF_REF_DIV_SEL.

1 VCM is fixed to AVDD5/2.

Address: 0x25, Reset: 0x00, Name: Diagnostic Control

Table 74. Bit Descriptions for Diagnostic Control

Bits

Bit Name

Settings

Description

Reset

Access

[7:6]

Reserved

Reserved.

0x0

ERR_OR_AIN_EN

Enables Overrange Monitor on all Enabled Analog Input Channels.

0x0

R/W

0 Input overvoltage monitor is disabled.

1 Input overvoltage monitor is enabled.

Reserved

0x0

MCLK_CNT_EN

Enables Master Clock Counter. Starts the MCLK counter, which monitors the external clock being

used by the ADC.

0x0

R/W

0 Disables MCLK counter.

1 Enables MCLK counter.

ERR_SPI_CRC_EN

Enables CRC Check on SPI Read and Write Operations. The ERR_SPI_CRC bit in the SPI error

operations.

0x0

R/W

0 SPI CRC disabled.

1 SPI CRC enabled.

ERR_MM_CRC_EN

Enables Memory Map CRC Calculation. CRC calculation is performed on the memory map each

time the registers are written to. Following this write, periodic CRC checks are performed on the

on-chip registers. If the register contents have changed, the ERR_MM_CRC bit is set.

0x0

R/W

0 Disables memory map CRC check.

1 Enables memory map CRC check.

FUSE_CRC_CHECK

Initiates a CRC Calculation on the Fuse Contents. If the fuse contents have changed, the

ERR_FUSE_CRC bit is set. This bit is cleared on completion of the check.

0x0

R/W

0 CRC calculation disabled.

1 CRC calculation enabled.

Address: 0x26, Reset: 0x00, Name: MPC_CONFIG

Table 75. Bit Descriptions for MPC_CONFIG

Bits

Bit Name

Settings

Description

Reset

Access

[7:6]

MPC_CLKDEL_EN_CH3

Magnitude and Phase Matching Calibration Clock Delay Enable for Channel 3.

0x0

R/W

00 Magnitude and phase clock delay: 0 clock delays.

01 Magnitude and phase clock delay: 1 clock delay.

10 Magnitude and phase clock delay: 2 clock delays.

11 Magnitude and phase clock delay: 0 clock delays.

[5:4]

MPC_CLKDEL_EN_CH2

Magnitude and Phase Matching Calibration Clock Delay Enable for Channel 2.

0x0

R/W

00 Magnitude and phase clock delay: 0 clock delays.

01 Magnitude and phase clock delay: 1 clock delay.

10 Magnitude and phase clock delay: 2 clock delays.

11 Magnitude and phase clock delay: 0 clock delays.

[3:2]

MPC_CLKDEL_EN_CH1

Magnitude and Phase Matching Calibration Clock Delay Enable for Channel 1.

0x0

R/W

AD4134 Datasheet(PDF) 86 Page - Analog Devices

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