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AD4134 Datasheet(PDF) 89 Page - Analog Devices |
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AD4134 Datasheet(HTML) 89 Page - Analog Devices |
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89 / 92 page  Data Sheet AD4134 REGISTER DETAILS analog.com Rev. 0 | 89 of 92 Table 92. Bit Descriptions for CH2_OFFSET_MID Bits Bit Name Settings Description Reset Access [7:0] OFFSET_CH2[15:8] Channel 2 Offset Calibration Value. 0x0 R/W Address: 0x38, Reset: 0x00, Name: CH2_OFFSET_MSB Table 93. Bit Descriptions for CH2_OFFSET_MSB Bits Bit Name Settings Description Reset Access 7 OFFSET_CAL_EN_CH2 Enables Offset Calibration on Channel 2. 0x0 R/W [6:0] OFFSET_CH2[22:16] Channel 2 Offset Calibration Value. 0x0 R/W Address: 0x39, Reset: 0x00, Name: CH3_GAIN_LSB Table 94. Bit Descriptions for CH3_GAIN_LSB Bits Bit Name Settings Description Reset Access [7:0] GAIN_CH3[7:0] Channel 3 Gain Calibration Value. 0x0 R/W Address: 0x3A, Reset: 0x00, Name: CH3_GAIN_MID Table 95. Bit Descriptions for CH3_GAIN_MID Bits Bit Name Settings Description Reset Access [7:0] GAIN_CH3[15:8] Channel 3 Gain Calibration Value. 0x0 R/W Address: 0x3B, Reset: 0x00, Name: CH3_GAIN_MSB Table 96. Bit Descriptions for CH3_GAIN_MSB Bits Bit Name Settings Description Reset Access [7:5] Reserved Reserved. 0x0 R 4 GAIN_CAL_SEL_CH3 Enables Gain Calibration on Channel 3. 0x0 R/W [3:0] GAIN_CH3[19:16] Channel 3 Gain Calibration Value. 0x0 R/W Address: 0x3C, Reset: 0x00, Name: CH3_OFFSET_LSB Table 97. Bit Descriptions for CH3_OFFSET_LSB Bits Bit Name Settings Description Reset Access [7:0] OFFSET_CH3[7:0] Channel 3 Offset Calibration Value. 0x0 R/W Address: 0x3D, Reset: 0x00, Name: CH3_OFFSET_MID Table 98. Bit Descriptions for CH3_OFFSET_MID Bits Bit Name Settings Description Reset Access [7:0] OFFSET_CH3[15:8] Channel 3 Offset Calibration Value. 0x0 R/W Address: 0x3E, Reset: 0x00, Name: CH3_OFFSET_MSB Table 99. Bit Descriptions for CH3_OFFSET_MSB Bits Bit Name Settings Description Reset Access 7 OFFSET_CAL_EN_CH3 Enables Offset Calibration on Channel 3. 0x0 R/W [6:0] OFFSET_CH3[22:16] Channel 3 Offset Calibration Value. 0x0 R/W Address: 0x3F, Reset: 0x00, Name: MCLK_COUNTER Table 100. Bit Descriptions for MCLK_COUNTER Bits Bit Name Settings Description Reset Access [7:0] MCLK_COUNT 8-Bit Counter that Increments Once Every 12,000 MCLK Cycles. The counter output is read back, which enables the user to determine the frequency of the external clock. The MCLK counter starts when MCLK_CNT_EN is set, and ends when it reaches 255 MCLK cycles. 0x0 R Address: 0x40, Reset: 0x00, Name: DIG_FILTER_OFUF |
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