AD4134 datasheet(15/92 Pages) AD

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Data Sheet

AD4134

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Table 8. Pin Function Descriptions

Pin No.

Mnemonic

Type1

Description

DEC1/DCLKMODE

Decimation Ratio Selection Input 1 in Pin Control Master Mode (DEC1). Tie this pin to IOVDD or to IOGND to set

the output data rate. See the Programming Output Data Rate and Clock section for more details.

DCLK Mode Control in Pin Control Slave Mode and in SPI Control Mode (DCLKMODE). Tie this pin high to IOVDD

to set DCLK to operate in free running mode. Tie this pin low to ground to set DCLK to operate in gated mode.

DEC0/DCLKIO

Decimation Ratio Selection Input 0 in Pin Control Master Mode (DEC0). Tie this pin to IOVDD or to IOGND to set

the output data rate. See the Programming Output Data Rate and Clock section for more details.

DCLK Pin I/O Direction Control in Pin Control Slave Mode and in SPI Control Mode (DCLKIO). In master mode,

tie this pin to IOVDD to configure DCLK as an output. In slave mode, tie this pin low to ground to set DCLK as an

input. When the DEC1/DCLKMODE pin is high (DCLK is in free running mode), the DCLKIO input is ignored and

the DCLK direction is always the same as the ODR pin.

DOUT3

DI/O

Data Output 3. The output data is synchronous to DCLK and framed by the ODR pin. In Daisy-Chaining

Configuration this pin functions as input taking data from downstream device.

DOUT2

DI/O

Data Output 2. The output data is synchronous to DCLK and framed by the ODR pin. In Daisy-Chaining

Configuration this pin functions as input taking data from downstream device.

DOUT1

Data Output 1. The output data is synchronous to DCLK and framed by the ODR pin.

DOUT0

Data Output 0. The output data is synchronous to DCLK and framed by the ODR pin.

DCLK

DI/O

ADC Conversion Data Clock. Conversion data on the DOUT0 pin to the DOUT3 pin is clocked out synchronously

by DCLK. In pin control master mode, DCLK is configured as an output operating in gated mode. In pin control

slave mode or in SPI control mode, the DCLK direction and mode of operation are determined by the DEC1/

DCLKMODE pin and DCLKIO pin. Refer to Table 29 for details. In master mode, DCLK frequency is programmable

through DCLKRATEx in pin control mode or the DATA_PACKET_CONFIG register in SPI control mode.

ODR

DI/O

Output Data Rate Control and Framing. The frequency of the ODR signal matches the ADC output data rate. The

edges of the ODR signal can be used to frame the conversion output data bit steam. In master mode, the ODR

pin is configured as an output with the pin-programmable and register-programmable frequency derived from the

device master clock. In slave mode, the ODR pin is configured as an input to allow the external clock to control the

ADC output data rate.

IOVDD

Digital I/O Supply. This pin sets the logic levels for all interface I/O pins.

IOGND

GND

I/O Interface Ground Reference.

FILTER0/GPIO4

DI/O

Digital Filter Type Selection Input 0 in Pin Control Mode (FILTER0). Tie this pin to IOVDD or to IOGND to select the

digital filter options. See the Programming Digital Filter section for more details.

General-Purpose Input/Output 4 in SPI Control Mode (GPIO4).

FILTER1/GPIO5

DI/O

Digital Filter Type Selection Input 1 in Pin Control Mode (FILTER1). Tie this pin to IOVDD or to IOGND to select the

digital filter options. See the Programming Digital Filter section for more details.

General-Purpose Input/Output 5 in SPI Control Mode (GPIO5).

FRAME0/GPIO6

DI/O

Conversion Output Data Frame Control Input 0 in Pin Control Mode (FRAME0). Tie this pin to IOVDD or to IOGND

to select the conversation output data frame. See the Data Frame section for more details.

General-Purpose Input/Output 6 in SPI Control Mode (GPIO6).

FRAME1/GPIO7

DI/O

Conversion Output Data Frame Control Input 1 in Pin Control Mode (FRAME1). Tie this pin to IOVDD or to IOGND

to select the conversation output data frame. See the Data Frame section for more details.

General-Purpose Input/Output 7 in SPI Control Mode (GPIO7).

DGND1V8

GND

Ground Reference for Digital Supply Voltage, 1.8 V.

DVDD1V8

Digital Supply Voltage, 1.8 V. The pin is supplied from an external source or the internal LDO regulator. In either

case, a decoupling capacitor of 10 µF is required between DVDD1V8 and DGND1V8.

AVDD1V8

Analog Supply Voltage 1.8 V. The pin is supplied from an external source or the internal LDO regulator. In either

case, a decoupling capacitor of 10 µF is required between AVDD1V8 and AGND1V8.

AGND1V8

GND

Ground Reference for Analog Supply Voltage, 1.8 V.

LDOIN

Input for Three Internal 1.8 V LDO Regulators Powering AVDD1V8, DVDD1V8, and CLKVDD. Tie this pin to

DVDD1V8 if an external power supply is used to power AVDD1V8, DVDD1V8, and CLKVDD. A 10 µF decoupling

capacitor is required between LDOIN and DGND1V8. See the On-Board LDO Regulators section for more details.

DGND5

GND

Ground Reference for Digital Supply Voltage, 5 V.

DVDD5

Digital Supply Voltage, 5 V. A decoupling capacitor of 10 µF is required between DVDD5 and DGND5.

AVDD5

Analog Supply Voltage, 5 V. A decoupling capacitor of 10 µF is required between AVDD5 and AGND5.

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