AD4134 datasheet(64/92 Pages) AD

64 / 92 page

Data Sheet

AD4134

DIGITAL INTERFACE

analog.com

Rev. 0 | 64 of 92

SPI CRC

The SPI CRC code is an optional feature. Enabling it allows the

user to improve transaction robustness on the SPI bus, for exam-

ple, in a noisy environment.

The SPI CRC is calculated with the x8 + x2 + x + 1 polynomial with

an initial seed value of 0xA5.

The SPI CRC achieves a Hamming distance of 4 with a maximum

word length of 119 bits.

3-Wire Isolated Mode

The AD4134 powers up in 3-wire isolated mode and a toggle on the

chip select line makes the AD4134 exit this mode. The chip select

line is not used and must be connected to ground. The SPI packet

is 24 bits, consisting of an 8-bit command and address, 8-bit data

(entity), and 8-bit CRC. See Figure 112 for 3-wire isolated mode.

Also note that a streaming register read or write is not supported in

this mode.

Figure 112. 3-Wire Isolated Mode

Additional SPI Features

The AD4134 provides the user several options to control the SPI.

Some of the features are listed in the Single Instruction Mode

section through the Master Slave Transfer Bit section.

Single Instruction Mode

When the SINGLE_INSTR bit is set, streaming is disabled and only

one read or write operation is performed regardless of the state of

the line. If this bit is set and remains asserted, the state machine

resets after the data byte as if it was deasserted and awaits the

next instruction. Single instruction mode forces each data byte to be

preceded with a new instruction even though the line has not been

deasserted. Single instruction mode also allows additional flexibility

in the usage of the pin if it is required for an application. The default

for this bit is set, resulting in streaming being enabled.

SPI Lock/Unlock

The AD4134 provides the user an option to lock the SPI by per-

forming an SPI write of 24 consecutive 1s. This write blocks the

SPI read/write access to registers. To unlock and reset, the user

must perform an SPI write of 23 1s and one 0. The status of the

SPI can be read by completing an SPI read to an SPI register

whose value is known. If the SPI is out of sync, the user initiates an

unlock and resets the SPI. At any point, if the SPI is not responding,

execute a lock and unlock. This unlock/lock does not affect any

data transaction in progress on the data interface and does not

affect the SDO behavior.

Figure 113. SPI Lock/Unlock and Reset

Stream Mode

Stream mode allows the user to consecutively access one or

more registers repeatedly without having to carry the overhead

associated with setting up the address each cycle. At the end of the

loop, the autogenerated address resets to the beginning address

and resumes counting until the last address is reached again.

The process continues as long as the is not deactivated. When is

deactivated, stream mode is terminated until started again by the

user.

The STREAM_MODE register is used to tell the device how many

consecutive registers are to be accessed in the stream mode. If this

in this register is not zero, when streaming is initiated, the value

in this register tells the address generator how many consecutive

addresses are to be written to or read from before looping back

to the beginning address. If the value in this address is 0x01,

the same address is written to or read from for the duration of

the stream event. If the value is 0x02, two consecutive addresses

are written (or read) for the duration. For example, if the stream

entry point is Address 0x10, Address 0x10 is the first address.

Address 0x11 is the second address. After this loop is complete,

the next autogenerated address is 0x10 and so on. This cycle

continues until terminated by the user by deasserting the line.

To initiate stream mode, the user must first set this register,

0x000E, with a nonzero value indicating how many addresses are

to be accessed. Any value between 0x01 and 0xFF is valid. Take

care that all addresses within this scope are suitable for streaming

because some addresses may be specified as do not change. Next,

begin the read or write cycle as usual.

Master Slave Transfer Bit

Bit 0 of the TRANSFER_REGISTER is used as the master slave

transfer bit, which is useful when a register is composed of multiple

bytes that must all be written simultaneously to prevent errone-

ous device operation. In master mode, the ODR_VAL_INT_x and

ODR_VAL_FLT_x registers need this implementation. When this bit

is set, multiple bytes of data that have been transferred using the

SPI are written at one time to the slave. Upon completion of the

transfer, the slave device clears this bit (autoclear), indicating to the

SPI master that the transfer completed and the slave data can be

read back if desired by the control program.

AD4134 Datasheet(PDF) 64 Page - Analog Devices

AD4134 Datasheet(HTML) 64 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92

Datasheet Download

Link URL