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AD4134 Datasheet(PDF) 47 Page - Analog Devices |
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AD4134 Datasheet(HTML) 47 Page - Analog Devices |
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47 / 92 page  Data Sheet AD4134 DEVICE CONTROL analog.com Rev. 0 | 47 of 92 SPI CONTROL MODE The AD4134 has a 4-wire SPI that is compatible with QSPI™, MICROWIRE®, and DSPs. Using the SPI, the user can access the ADC register map and control the AD4134. To use SPI control mode, the PIN/SPI pin of the AD4134 must be set to logic high. The SPI control operates as a 16-bit, 4-wire interface, allowing read and write access. The SPI serial control interface of the AD4134 is an independent path for controlling and monitoring the AD4134. There is no direct link to the data interface. The timing of ODR and DCLK is not directly related to the timing of the SPI control interface. Refer to the SPI section for more details. The SPI control mode allows the user to configure more features than the pin control mode and use the device fully. The additional features available in SPI control mode are the following: ► Full suite of diagnostic features ► More options for ODR select and DCLK frequency select in master mode ► XCLKOUT disable ► Option for wideband digital filter FIR 0.108 × ODR ► Digital interface reset ► Programmable gain, offset, and channel delay ► Sleep mode ► 2-channel averaging ► Additional inherent alias mode (AA2) ► Programmable ODR, ODR/2, ODR/4, and ODR/8 ► VCM pin output voltage programmability ► Per channel phase delay MULTIFUNCTION PINS The AD4134 has multifunction pins where the function of these pins changes depending on the selected control mode. Table 25 shows a summary of the multifunction pin functions in each mode of operation. Table 25. Multifunction Pin Function Summary Pin Mnemonic Pin Function in Pin Control Mode Pin Function in SPI Control Mode FORMAT0/CS ADC output channel format selection SPI FORMAT1/SCLK DEC3/SDO ASRC master mode decimation ratio selection DEC2/SDI DEC1/DCLKMODE ASRC master mode: decimation ratio selection DCLK mode selection (free running or gated) ASRC slave mode: DCLK mode selection (free running or gated) DEC0/DCLKIO ASRC master mode: decimation ratio selection, DCLK is output DCLK I/O direction selection (input or output) ASRC slave mode: tie pin low to set it as input DCLKRATE0/GPIO0 DCLK output frequency selection in ASRC master mode General-purpose I/O DCLKRATE1/GPIO1 DCLKRATE2/GPIO2 PWRMODE/GPIO3 Device power mode selection (high performance or low power mode) FILTER0/GPIO4 Digital filter type selection FILTER1/GPIO5 FRAME0/GPIO6 Output data frame selection FRAME1/GPIO7 |
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