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AD4134 Datasheet(PDF) 51 Page - Analog Devices

Part # AD4134
Description  24-Bit, 4-Channel Simultaneous Sampling 1.5 MSPS Precision Alias Free ADC
PDF  92 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD4134 Datasheet(HTML) 51 Page - Analog Devices

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Data Sheet
AD4134
DEVICE CONFIGURATION
analog.com
Rev. 0 | 51 of 92
Data Clock (DCLK)
The data clock can be either an input or an output depending
on the direction of the ODR pin. When ODR is output for master
mode, set the DEC0/DCLKIO pin high to configure DCLK as an
output. When ODR is input for slave mode, tie the DEC0/DCLKIO
pin low to configure DCLK as an input. The data clock can be
operated in gated mode or free running mode controlled by the
DEC1/DCLKMODE pin.
When operated in pin control mode with the ASRC set to master
mode, the DCLK operation is limited to gated output only. When
operating in pin control mode with the ASRC set to slave mode, or
when operating in SPI control mode, the DCLK mode of operation
is controlled by the DEC1/DCLKMODE pin and DEC0/DCLKIO pin,
as shown in Table 29.
In master mode, the DCLK pin is configured as an output. The
DCLK frequency is derived from the AD4134 device master clock
and can be configured using the DCLKRATE0/GPIO0 pin to
DCLKRATE2/GPIO2 pin in pin control mode, or DCLK_ FREQ_SEL
(Bits[3:0]) in Register 0x11 in SPI control mode. SPI control mode
offers 16 DCLK output frequency options, and pin control mode
offers eight. Table 30 lists all the DCLK output frequency options.
In slave mode, the DCLK pin is an external signal.
Table 29. DCLK Mode of Operation in Pin Control Mode or in SPI Control Mode
DEC1/DCLKMODE
DEC0/DCLKIO
MODE
DCLK Direction
DCLK Mode
0
0
0
Input
Gated
0
0
1
Reserved
Reserved
0
1
0
Reserved
Reserved
0
1
1
Output
Gated
1
0
0
Input
Free running
1
0
1
Reserved
Reserved
1
1
0
Reserved
Reserved
1
1
1
Output
Free running
Table 30. DCLK Output Frequency Configuration
DCLKRATE2 or Register 0x11,
Bit 3
DCLKRATE1 or
Register 0x11, Bit 2
DCLKRATE0 or
Register 0x11, Bit 1
Register 0x11, Bit 0
DCLK Output Frequency Options
0
0
0
0
48 MHz (SPI/pin control mode default)
0
0
0
1
24 MHz1
0
0
1
0
12 MHz
0
0
1
1
6 MHz1
0
1
0
0
3 MHz
0
1
0
1
1.5 MHz1
0
1
1
0
750 kHz
0
1
1
1
375 kHz1
1
0
0
0
187.5 kHz
1
0
0
1
93.75 kHz1
1
0
1
0
46.875 kHz
1
0
1
1
234.375 kHz1
1
1
0
0
11.71875 kHz
1
1
0
1
5.859375 kHz1
1
1
1
0
2.929688 kHz
1
1
1
1
1.464844 kHz1
1 Not available in pin control mode.



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