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AD4134 Datasheet(PDF) 10 Page - Analog Devices |
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AD4134 Datasheet(HTML) 10 Page - Analog Devices |
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10 / 92 page  Data Sheet AD4134 SPECIFICATIONS analog.com Rev. 0 | 10 of 92 Table 1. Parameter Test Conditions/Comments Min Typ Max Unit 4 For slave mode, the maximum ODR supported for the sinc3 filter is 1460 kSPS. 5 Excluding the first five harmonics. 6 Following a full system calibration, the offset error and the gain error are in the order of the noise for the programmed output data rate selected. The gain error is a function of the output data rate in slave mode. Therefore, a gain error calibration is needed when the output data rate is changed. It is recommended to perform a periodic system calibration to stop aging related drifts. 7 Between any two channels on the same device. 8 Between any two channels on any two devices. SPI slave mode with DCLK as gated input only with the DIG_IF_RESET SPI write issued simultaneously to both devices. TIMING SPECIFICATIONS AVDD5 = DVDD5 = 4.5 V to 5.5 V, AVDD1V8 = DVDD1V8 = 1.65 V to 1.95 V, CLKVDD = 1.65 V to 1.95 V, IOVDD = 1.65 V to 1.95 V, CLKIN = 48 MHz, AGND5 = DGND5 = AGND1V8 = DGND1V8 = IOGND = CLKGND = 0 V, TA = −40°C to 105°C, unless otherwise noted. Typical values are at TA = 25°C, unless otherwise noted. Table 2. Device Clock Timing Parameter Description Test Conditions/Comments Min Typ Max Unit fSYSCLK System clock frequency 48 MHz MCLK Master clock High performance mode fSYSCLK/2 Hz Low power mode fSYSCLK/4 Hz fDIGCLK Internal digital clock (tDIGCLK) = 1/fDIGCLK fSYSCLK/2 Hz fDCLK Data Interface clock (tDCLK) = 1/fDCLK DCLK as output, SPI control mode fSYSCLK MHz DCLK as output, pin control mode fSYSCLK MHz DCLK as input 50 MHz fSCLK SPI clock rate (tSCLK) = 1/fSCLK 50 MHz The signal on DOUTx is driven out on the rising edge of the DCLK. tODR_PERIOD is 1/ODR. See Figure 2. Table 3. Data Interface Timing with Gated DCLK Parameter Description Test Conditions/Comments Min Typ Max Unit t1 ODR high time Master mode, tDCLK > tDIGCLK 2.5 × tDCLK 3.5 × tDCLK ns Master mode, tDCLK ≤ tDIGCLK 3 × tDIGCLK 3 × tDIGCLK + 4 ns Slave mode 3 × tDIGCLK ns t2 ODR low time Slave mode 3 × tDIGCLK ns t3 ODR falling edge to DCLK rising edge Master mode tDCLK − 2 ns Slave mode 8 ns t4 Last data DCLK falling edge to ODR rising edge Slave mode 2 × tDCLK ns t5 DCLK rising to DOUTx invalid Master mode −4 ns Slave mode 0 ns t6 DCLK rising to DOUTx valid Master mode 0 3 ns Slave mode 8.2 ns t7 DCLK low time tDCLK/2 − 1 ns t8 DCLK high time tDCLK/2 − 1 ns |
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