AD4134 datasheet(45/92 Pages) AD

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Data Sheet

AD4134

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STANDALONE MODE

The user has a digital host without an SPI and needs a −3 dB input

bandwidth of 102.4 kHz. The user also desires a flat pass-band

response with robust data interface. The recommended scheme is

pin controlled master mode. The 102.4 kHz input bandwidth with

flat pass band can be achieved by using a 0.433 × ODR FIR filter.

The minimum ODR needed can be calculated as input bandwidth

= 0.433 × ODR. Therefore, the minimum ODR needed is 237

kSPS. From Table 28, the closest ODR value of 256 kSPS can be

programmed.

The robust interface calls for using the cyclic redundancy check

(CRC). Therefore, the frame size is 24 data bits + 8-bit header that

includes a 6-bit CRC and a 2-bit status.

The DCLK value required is >(Frame Size + 6) × ODR, giving the

user a value of 9.7 MHz. From Table 30, the closest DCLK option is

12 MHz.

The settings to be configured are pin control mode control, ASRC

master, high performance mode, gated DCLK output, 32-bit frame,

256 kSPS ODR, 12 MHz DCLK, 0.433 × ODR filter, external LDO

regulator, and 4-channel output.

Refer to the Device Configuration section for programming these

settings.

Table 21. Configuration 1 Hardware Settings

Pin Function

Supply/Level

Comments

AVDD5, DVDD5

5 V

Supply

IOVDD, LDOIN, AVDD1V8,

DVDD1V8, CLKVDD

1.8 V

Supply

PIN/SPI

Low

Pin control

CLKSEL

High

Crystal input

MODE

High

ASRC master

DCLKMODE

Low

Gated DCLK

DCLKIO

High

DCLK output

FILTER1, FILTER0

Low, low

0.433 × ODR filter

FORMAT1, FORMAT0

High, low

4-channel output

FRAME1, FRAME0

High, high

32-bit output

PWRMODE

High

High performance

DCLKRATE2, DCLKRATE1,

DCLKRATE0

Low, low, high

12 MHz DCLK

DEC3, DEC2, DEC1, DEC0

Low, low, high, high

256 kSPS ODR

LOW LATENCY SYNCHRONOUS DATA

ACQUISITION

The user has an input signal bandwidth of 250 kHz and needs a

24-bit output with minimum latency. There are eight channels and

the user needs tight synchronization between the channels.

The recommended scheme is to use two devices in SPI controlled

slave mode. The external ODR signal can synchronize both devices

with a digital interface reset issued simultaneously. See the Multide-

vice Synchronization section for more details.

The 250 kHz input bandwidth with minimum latency can be ach-

ieved by the sinc3 filter. The minimum ODR needed can be calcu-

lated as input bandwidth = 0.2617 × ODR. Therefore, the ODR

required is 956 kSPS.

The external DCLK value required is >(Frame Size + 6) × ODR,

giving the user a value of 29 MHz. Provide the DCLK and ODR

values as per the timing specifications listed in Table 3.

The settings to be configured are SPI control mode control, ASRC

slave, high performance mode, gated DCLK input, 24-bit data

output, 956 kSPS ODR, 29 MHz DCLK, sinc3 filter, external LDO

regulator, and 4-channel output.

Refer to the Device Configuration section for programming these

settings. After power-on, verify the hardware configuration by read-

ing the DEVICE_STATUS register.

Table 22. Configuration 2 Hardware Settings

Pin Function

Supply/Level

Comments

AVDD5, DVDD5

5 V

Supply

IOVDD, CLKVDD, AVDD1V8, LDOIN,

DVDD1V8

1.8 V

Supply

PIN/SPI

High

SPI control

mode

CLKSEL

High

Crystal input

MODE

Low

ASRC slave

DCLKMODE

Low

Gated DCLK

DCLKIO

Low

DCLK input

Program the registers in Table 23 with the values listed and leave

the all the other registers at their default values.

Table 23. Software Settings

SPI Register

Value

Comments

DATA_PACKET_CONFIG

0x20

24-bit frame

DEVICE_CONFIG

0x01

High performance mode

CHAN_DIG_FILTER_SEL

0xAA

Sinc3 filter

DIGITAL_INTERFACE_CONFIG

0x03

4-channel parallel

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