AD4134 datasheet(81/92 Pages) AD

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Data Sheet

AD4134

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Rev. 0 | 81 of 92

Table 55. Bit Descriptions for DIGITAL_INTERFACE_CONFIG

Bits

Bit Name

Settings

Description

Reset

Access

10 Data from Channel 2 and Channel 3 are averaged and output on DOUT2. DOUT3 is

disabled. Channel 0 and Channel 1 are under normal operation.

11 Data from Channel 0 and Channel 1 are averaged and output on DOUT0. Data from

Channel 2 and Channel 3 are averaged and output on DOUT1. DOUT2 and DOUT3 act

as daisy-chain inputs.

[1:0]

Format

DOUTx Output Format Configuration.

0x0

R/W

0 Single-channel daisy-chain mode. DOUT0 acts as an output and DOUT2 acts as a

daisy-chain input. DOUT1 and DOUT3 are disabled. Data from all four ADC channels

are output on DOUT0.

1 Dual-channel daisy-chain mode. DOUT0 and DOUT1 act as output and DOUT2 and

DOUT3 act as daisy-chain input. Data from Channel 0 and Channel 1 are output on

DOUT0. Data from Channel 2 and Channel 3 are output on DOUT1.

10 Quad channel parallel output mode. Each ADC channel has a dedicated data output

pin.

11 Channel data averaging mode, averaging operation is defined by AVG_SEL.

Address: 0x13, Reset: 0x00, Name: POWER_DOWN_CONTROL

Table 56. Bit Descriptions for POWER_DOWN_CONTROL

Bits

Bit Name

Settings

Description

Reset

Access

Reserved

Reserved.

0x0

PWRDN_CH3

Powers Down Analog Input Channel 3.

0x0

R/W

0 Power up.

1 Power down.

PWRDN_CH2

Powers Down Analog Input Channel 2.

0x0

R/W

0 Power up.

1 Power down.

PWRDN_CH1

Powers Down Analog Input Channel 1.

0x0

R/W

0 Power up.

1 Power down.

PWRDN_CH0

Powers Down Analog Input Channel 0.

0x0

R/W

0 Power up.

1 Power down.

Reserved

Reserved.

0x0

PWRDN_LDO

Powers Down the Internal Analog and Clock LDO Regulators.

0x0

R/W

0 Internal LDO regulators powered.

1 Internal LDO regulators powered down.

SLEEP_MODE_EN

All Blocks Except Digital LDO Regulator are Turned Off. On-chip register contents remain the

same.

0x0

R/W

0 Sleep mode disabled.

1 Sleep mode enabled.

Address: 0x14, Reset: 0x00, Name: RESERVED

Table 57. Bit Descriptions for RESERVED

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

Reserved

Reserved. Always zero.

0x0

R/W

Address: 0x15, Reset: 0x00, Name: DEVICE_STATUS

Table 58. Bit Descriptions for DEVICE_STATUS

Bits

Bit Name

Settings

Description

Reset

Access

[7:6]

Reserved

Reserved.

0x0

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