AD4134 datasheet(53/92 Pages) AD

53 / 92 page

Data Sheet

AD4134

DEVICE CONFIGURATION

analog.com

Rev. 0 | 53 of 92

PROGRAMMING DATA INTERFACE

The digital interface consists of setting up the format, the frame,

and the averaging options.

Output Channel Format

The data interface format is determined by setting the FOR-

MAT0/CS pin and FORMAT1/SCLK pin. The logic state of the

FORMAT0/CS pin and FORMAT1/SCLK pin is read on power-up

and determine how many data lines (DOUTx) the ADC conversions

are output on.

Because the FORMAT0/CS pin and FORMAT1/SCLK pin are read

on power-up of the AD4134 and the device remains in this output

configuration, this function must always be hardwired and cannot

be altered dynamically. Figure 90 and Figure 91 show the format-

ting configuration for the digital output pins on the AD4134.

Calculate the minimum required DCLK rate for a given data inter-

face configuration as follows:

DCLK (Minimum) = Output Data Rate × Channels per DOUTx ×

(Frame Size + 6)

For example, if data size = 24 and 6-bit CRC is enabled with one

DOUTx line, single-channel daisy-chaining,

DCLK (Minimum) = 374 kSPS × 4 Channels per DOUTx × (24 + 8 +

6) = 44.88 Mbps

The AD4134 can output the data from four ADC channels in parallel

using four output pins, or serialize the data and output them using

fewer pins. Paralleling the output enables a higher output data

rate for a given DCLK frequency. In addition to using fewer I/Os,

serializing the data allows data from multiple AD4134 devices to be

daisy-chained.

The output channel format is controlled by the FORMAT0/ pin and

FORMAT1/SCLK pin in pin control mode and the format bits in the

DIGITAL_INTERFACE_CONFIG register in SPI control mode.

Table 32 lists all the output channel format options.

Figure 90. FORMAT1, FORMAT0 = 10, Four Data Output Pins

Figure 91. FORMAT1, FORMAT0 = 00, One Data Output Pin

Table 32. Output Channel Format Configuration

FORMAT1/SCLK Pin or Bit 1,

DIGITAL_INTERFACE_CONFIG

FORMAT0/ Pin or Bit 0,

DIGITAL_INTERFACE_CONFI

G Register

Output Channel Format

Single-channel daisy-chain mode. DOUT0 acts as an output and DOUT2 acts as a daisy-chain input.

DOUT1 and DOUT3 are disabled. Data from all four ADC channels are serialized and output on DOUT0

(SPI default mode).

Dual-channel daisy-chain mode. DOUT0 and DOUT1 act as outputs, and DOUT2 and DOUT3 act as

daisy-chain inputs. Data from Channel 0 and Channel 1 are serialized and output on DOUT0. Data from

Channel 2 and Channel 3 are serialized and output on DOUT1.

Quad-channel parallel output mode. Each ADC channel has a dedicated data output pin.

Channel data averaging mode. In pin control mode, data from all four channels are averaged and output

on DOUT0. DOUT2 acts as daisy-chain input. DOUT1 and DOUT3 are disabled. In SPI control mode, the

averaging operation is defined by the AVG_SEL bits in Register 0x12.

AD4134 Datasheet(PDF) 53 Page - Analog Devices

AD4134 Datasheet(HTML) 53 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92

Datasheet Download

Link URL