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AD4134 Datasheet(PDF) 84 Page - Analog Devices |
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AD4134 Datasheet(HTML) 84 Page - Analog Devices |
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84 / 92 page  Data Sheet AD4134 REGISTER DETAILS analog.com Rev. 0 | 84 of 92 Table 67. Bit Descriptions for CHAN_DIG_FILTER_SEL Bits Bit Name Settings Description Reset Access 10 Sinc3 filter. 11 Sinc3 filter with simultaneous 50 Hz and 60 Hz rejection. [1:0] DIGFILTER_SEL_CH0 Channel 0 Digital Filter Type Selection. 0x0 R/W 0 Wideband filter. 01 Sinc6 filter. 10 Sinc3 filter. 11 Sinc3 filter with simultaneous 50 Hz and 60 Hz rejection. Address: 0x1F, Reset: 0x00, Name: FIR_BW_SEL Table 68. Bit Descriptions for FIR_BW_SEL Bits Bit Name Settings Description Reset Access [7:4] Reserved Reserved. 0x0 R 3 WB_FILTER_SEL_CH3 Channel 3 Wideband Filter Bandwidth Selection. 0x0 R/W 0 Wideband filter has a bandwidth of 0.433 × ODR. 1 Wideband filter has a bandwidth of 0.10825 × ODR. 2 WB_FILTER_SEL_CH2 Channel 2 Wideband Filter Bandwidth Selection. 0x0 R/W 0 Wideband filter has a bandwidth of 0.433 × ODR. 1 Wideband filter has a bandwidth of 0.10825 × ODR. 1 WB_FILTER_SEL_CH1 Channel 1 Wideband Filter Bandwidth Selection. 0x0 R/W 0 Wideband filter has a bandwidth of 0.433 × ODR. 1 Wideband filter has a bandwidth of 0.10825 × ODR. 0 WB_FILTER_SEL_CH0 Channel 0 Wideband Filter Bandwidth Selection. 0x0 R/W 0 Wideband filter has a bandwidth of 0.433 × ODR. 1 Wideband filter has a bandwidth of 0.10825 × ODR. Address: 0x20, Reset: 0x00, Name: GPIO_DIR_CTRL Table 69. Bit Descriptions for GPIO_DIR_CTRL Bits Bit Name Settings Description Reset Access [7:0] GPIO_IO_CONTROL GPIO I/O Direction Control. Each bit controls the direction of a GPIO pin. A value of 0 sets the GPIO pin as an input. A value of 1 sets the GPIO pin as an output. Bit 0 is associated with GPIO0. 0x0 R/W Address: 0x21, Reset: 0x00, Name: GPIO_DATA Table 70. Bit Descriptions for GPIO_DATA Bits Bit Name Settings Description Reset Access [7:0] GPIO_DATA GPIO Data Value. If a GPIO pin is configured as an input, the corresponding bit is read only and its value reflects the input logic status of the pin. If a GPIO pin is configured as an output, write to the corresponding bit to control the output logic of the pin. Bit 0 is associated with GPIO0. 1 = logic high and 0 = logic low. 0x0 R/W Address: 0x22, Reset: 0x00, Name: ERROR_PIN_SRC_CON-TROL Table 71. Bit Descriptions for ERROR_PIN_SRC_CONTROL Bits Bit Name Settings Description Reset Access [7:6] Reserved Reserved. 0x0 R 5 ERR_PIN_EN_OR_AIN Enables Error Reporting on GPIO7 for Input Overrange Errors. 0x0 R/W 0 Disables pin toggle for overvoltage error. 1 Enables pin toggle for overvoltage error. 4 ERR_PIN_EN_INTERNAL Enables Error Reporting on GPIO7 for Any Internal Errors. Internal error can be digital overflow or underflow error, memory map CRC error, ASRC error, fuse CRC error, or 0x0 R/W |
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