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AD4134 Datasheet(PDF) 77 Page - Analog Devices

Part # AD4134
Description  24-Bit, 4-Channel Simultaneous Sampling 1.5 MSPS Precision Alias Free ADC
PDF  92 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD4134 Datasheet(HTML) 77 Page - Analog Devices

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Data Sheet
AD4134
REGISTER DETAILS
analog.com
Rev. 0 | 77 of 92
Address: 0x0, Reset: 0x18, Name: INTERFACE_CONFIG_A
Table 39. Bit Descriptions for INTERFACE_CONFIG_A
Bits
Bit Name
Settings
Description
Reset
Access
7
SOFT_RESET
Soft Reset of the Device. This bit is cleared on completion of a reset.
0x0
R/W
0 Default.
1 Initiates a soft reset.
6
Reserved
Reserved.
0x0
R
5
ADDRESS_ASCENSION_BIT
Register Map Address Ascension/Descend Control. Used with streaming
mode, address ascension causes sequential register addresses to ascend
in order. Disabling causes sequential register addresses to descend in
order.
0x0
R/W
0 Sequential register address in descending order.
1 Sequential register address in ascending order.
4
SDO_ACTIVE_BIT
SDO Control.
0x1
R/W
0 SDO disabled, exhibit high impedance.
1 SDO enabled.
3
SDO_ACTIVE_BIT_MIRROR
Mirror Image of SDO_ACTIVE_BIT.
0x1
R
2
ADDRESS_ASCENSION_BIT_MIRROR
Mirror Image of ADDRESS_ASCENTION_BIT.
0x0
R
1
Reserved
Reserved.
0x0
R
0
SOFT_RESET_MIRROR
Mirror Image of SOFT_RESET.
0x0
R/W
0 Default.
1 Initiates a soft reset.
Address: 0x1, Reset: 0x80, Name: INTERFACE_CONFIG_B
Table 40. Bit Descriptions for INTERFACE_CONFIG_B
Bits
Bit Name
Settings
Description
Reset
Access
7
SINGLE_INSTR
Single Instruction Mode Control. When set, this bit disables streaming regardless of the
state of . When clear, streaming is enabled.
0x1
R/W
0 Disable.
1 Enable.
6
Reserved
Reserved.
0x0
R
5
MASTER_SLAVE_RD_CTRL
Master Slave Readback Control. Determines the data to read back from the master
or slave buffered bits (ODR_VAL_INT_x and ODR_VAL_FLT_x). Set to 1 to read back
from master output. Clear this bit to read back from slave output.
0x0
R/W
0 Readback of the slave flip flop outputs.
1 Readback of the master flip flop outputs.
[4:2]
Reserved
Reserved.
0x0
R
1
DIG_IF_RESET
Digital Interface Reset.
0x0
R/W
0
Reserved
Reserved.
0x0
R/W
Address: 0x2, Reset: 0xD0, Name: DEVICE_CONFIG
Table 41. Bit Descriptions for DEVICE_CONFIG
Bits
Bit Name
Settings
Description
Reset
Access
[7:6]
Reserved
Reserved.
0x3
R
5
OP_IN_PROGRESS
Operation in Progress Indicator. A readback value of 0 indicates that the device is busy.
0x0
R
0 Some operation in progress.
1 No operation in progress.
4
NO_CHIP_ERR
Error Flag for all of the Enabled Status Errors. This bit is the OR of all the enabled error bits and
continues to stay clear as long as any error flag is set.
0x1
R
0 Device has a chip error.
1 No chip error.



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