AD4134 datasheet(66/92 Pages) AD

66 / 92 page

Data Sheet

AD4134

DIGITAL INTERFACE

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Rev. 0 | 66 of 92

Figure 115. Data CRC Options

ASRC Master Mode Data Interface

When the ASRC is in master mode, the ODR pin behaves as an

output. The user has the choice to operate the DCLK pin in gated

mode or in free running mode.

With the DCLK pin configured as an output, the AD4134 acts as the

data interface master, providing the DCLK signals and the output

data steam synchronously to the ODR signal.

Figure 116. Data Interface Example 1, First AD4134 Device in ASRC Master

Mode with the Digital Host as Interface Slave

ASRC Slave Mode Data Interface

When the ASRC is in slave mode, the ODR pin behaves as an

input. The user has the choice to operate the DCLK pin in gated

mode or in free running mode.

With the DCLK pin configured as an input, the AD4134 acts as the

data interface slave, providing the output data stream on the input

DCLK driving edge.

If the DCLK pin is configured as a free running input, the user must

ensure that the DCLK pin is synchronized to the ODR signal for

proper data framing.

Figure 117. Data interface Example 2, Two AD4134 Devices in ASRC Slave

Mode with Digital Host as Interface Master

Daisy-Chaining

Daisy-chaining allows numerous devices to use the same data

interface lines by cascading the outputs of multiple ADCs from

separate AD4134 devices. The data interface of only one ADC

device is in direct connection with the digital host.

For the AD4134, implement this connection by cascading DOUT0

and DOUT1 through a number of devices, or using only DOUT0.

This feature is especially useful for reducing component count and

wiring connections, for example, in isolated multiconverter applica-

tions or for systems with a limited interfacing capacity.

When daisy-chaining with two channels, DOUT2 and DOUT3 be-

come serial data inputs, and DOUT0 and DOUT1 remain as serial

data outputs.

Figure 118 shows an example of daisy-chaining the AD4134 devi-

ces with two channels. In this case, the DOUT0 pin and DOUT1 pin

of the AD4134 devices are cascaded to the DOUT2 and DOUT3

pins of the next device in the chain. Data readback is analogous to

clocking a shift register.

The scheme operates by passing the output data of the DOUT0 pin

and DOUT1 pin of an AD4134 downstream device to the DOUT2

and DOUT3 inputs of the next AD4134 device upstream in the

chain. The data then continues through the chain until it is clocked

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