AD4134 datasheet(79/92 Pages) AD

79 / 92 page

Data Sheet

AD4134

analog.com

Rev. 0 | 79 of 92

Address: 0xD, Reset: 0x04, Name: VENDOR_ID_MSB

Table 50. Bit Descriptions for VENDOR_ID_MSB

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

VENDOR_ID[15:8]

Vendor ID.

0x4

Address: 0xE, Reset: 0x00, Name: STREAM_MODE

Table 51. Bit Descriptions for STREAM_MODE

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

STREAM_MODE_BITS

Defines the Depth of the Loop for User Stream Mode.

0x0

R/W

Address: 0xF, Reset: 0x00, Name: TRANSFER_REGISTER

Table 52. Bit Descriptions for TRANSFER_REGISTER

Bits

Bit Name

Settings

Description

Reset

Access

[7:1]

Reserved

Reserved.

0x0

MASTER_SLAVE_TX_BIT

Master Slave Transfer Bit. When this bit is set, data is entered into the master registers

transferred to the slave. Upon completion of the transfer, the slave device clears this bit

(autoclears), indicating to the SPI master that the transfer was complete and the slave

data can be read back if desired by the control program. Prior to a transfer, an attempted

readback views the prior data unless Bit 5 of Register 0x1 (MASTER_SLAVE_RD_CTRL)

is set. In that case, the master data is accessed. Another method to invoke the transfer is

to use the low to high transition.

0x0

R/W

Address: 0x10, Reset: 0x00, Name: DEVICE_CONFIG_1

Table 53. Bit Descriptions for DEVICE_CONFIG_1

Bits

Bit Name

Settings

Description

Reset

Access

[7:4]

Reserved

Reserved, is always zero.

0x0

R/W

AA_MODE

Sets Inherent Antialiasing Mode.

0x0

R/W

0 AA1 mode.

1 AA2 mode.

SDO_PIN_SRC_SEL

DEC3/SDO Pin Signal Source Selection. In minimum I/O mode, the user can use the

DEC3/SDO pin for both register content and ADC conversion data readback.

0x0

R/W

0 DEC3/SDO pin acts as SPI serial data output.

1 Signal on DOUT0 is duplicated on DEC3/SDO pin.

REFIN_GAIN_CORR_EN

Enables Reference Gain Correction.

0x0

R/W

0 Reference gain correction disabled.

1 Reference gain correction enabled.

XCLKOUT_EN

XCLKOUT Output Enable Control.

0x0

R/W

0 XCLKOUT disabled.

1 XCLKOUT enabled.

Address: 0x11, Reset: 0x00, Name: DATA_PACKET_CONFIG

Table 54. Bit Descriptions for DATA_PACKET_CONFIG

Bits

Bit Name

Settings

Description

Reset

Access

CRC_POLY_RST_SEL

Data Interface CRC Reset Method Selection.

0x0

R/W

0 The data interface CRC is reset with default seed value at the end of every data frame.

1 The data interface CRC does not reset at the end of each data frame. The CRC value

calculated from the proceeding data frame seeds the CRC calculation of the current data

frame.

Reserved

Reserved - Please write 0 to this bit always

0x0

R/W

[5:4]

Frame

ADC Conversion Data Output Frame Control.

0x0

R/W

0 16-bit ADC data only.

1 16-bit ADC data followed by 6-bit CRC.

AD4134 Datasheet(PDF) 79 Page - Analog Devices

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