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AD4134 Datasheet(PDF) 82 Page - Analog Devices |
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AD4134 Datasheet(HTML) 82 Page - Analog Devices |
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82 / 92 page  Data Sheet AD4134 REGISTER DETAILS analog.com Rev. 0 | 82 of 92 Table 58. Bit Descriptions for DEVICE_STATUS Bits Bit Name Settings Description Reset Access 5 STAT_DCLKMODE DEC1/DCLKMODE Pin Status Indicates if DCLK is in Free Running or Gated Mode. 0x0 R 0 DCLK is in gated mode. Compatible with SPI interface. 1 DCLK is in free running mode. 4 STAT_DCLKIO DEC0/DCLKIO Pin Status Indicates DCLK Pin Direction. 0x0 R 0 DCLK is input. 1 DCLK is output. 3 STAT_MODE MODE Pin Status Indicates Whether Device is Master or Slave. 0x0 R 0 Slave mode: ODR is input. 1 Master mode: ODR is output. 2 STAT_CLKSEL CLKSEL Pin Status Indicates the Clock Source. 0x0 R 0 CMOS input clock is connected. 1 Crystal input is connected. 1 STAT_FUSE_ECC Status Bit that Indicates Application of Fuse Error Correction Code. This bit is cleared on is read. 0x0 R 0 Error code correction not applied. 1 Error code correction applied. 0 STAT_PLL_LOCK PLL Status in Slave Mode. Indicates if PLL has locked or not. Setting this bit indicates PLL is locked. 0x0 R 0 PLL not locked. 1 PLL locked. Address: 0x16, Reset: 0x40, Name: ODR_VAL_INT_LSB Table 59. Bit Descriptions for ODR_VAL_INT_LSB Bits Bit Name Settings Description Reset Access [7:0] ODR_VAL_INT[7:0] Integer Portion of Decimation Rate. Decimation rate is the ratio of 24 MHz to ODR. In master mode, the user can program this register to set the ODR output frequency. 0x40 R/W Address: 0x17, Reset: 0x00, Name: ODR_VAL_INT_MID Table 60. Bit Descriptions for ODR_VAL_INT_MID Bits Bit Name Settings Description Reset Access [7:0] ODR_VAL_INT[15:8] Integer Portion of Decimation Rate. Decimation rate is the ratio of 24 MHz to ODR. In master mode, the user can program this register to set the ODR output frequency. 0x0 R/W Address: 0x18, Reset: 0x00, Name: ODR_VAL_INT_MSB Table 61. Bit Descriptions for ODR_VAL_INT_MSB Bits Bit Name Settings Description Reset Access [7:0] ODR_VAL_INT[23:16] Integer Portion of Decimation Rate. Decimation rate is the ratio of 24 MHz to ODR. In master mode, the user can program this register to set the ODR output frequency. 0x0 R/W Address: 0x19, Reset: 0x72, Name: ODR_VAL_FLT_LSB Table 62. Bit Descriptions for ODR_VAL_FLT_LSB Bits Bit Name Settings Description Reset Access [7:0] ODR_VAL_FLT[7:0] Fractional Portion of Decimation Rate. Decimation rate is the ratio of 24 MHz to ODR. In master mode, the user can program this register to set the ODR output frequency. 0x72 R/W Address: 0x1A, Reset: 0xB7, Name: ODR_VAL_FLT_MID0 Table 63. Bit Descriptions for ODR_VAL_FLT_MID0 Bits Bit Name Settings Description Reset Access [7:0] ODR_VAL_FLT[15:8] Fractional Portion of Decimation Rate. Decimation rate is the ratio of 24 MHz to ODR. In master mode, the user can program this register to set the ODR output frequency. 0xB7 R/W Address: 0x1B, Reset: 0xCE, Name: ODR_VAL_FLT_MID1 |
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