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SC1100 Datasheet(PDF) 20 Page - National Semiconductor (TI) |
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SC1100 Datasheet(HTML) 20 Page - National Semiconductor (TI) |
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20 / 348 page ![]() www.national.com 20 Revision 1.1 Signal Definitions (Continued) C8 2 MD53 I/O INT, TS2/5 VIO --- C9 2 MD55 I/O INT, TS2/5 VIO --- C10 MA7 O O2/5 VIO --- C11 BA0 O O2/5 VIO --- C12 BA1 O O2/5 VIO --- C13 MA11 O O2/5 VIO --- C14 DQM6 O O2/5 VIO --- C15 DQM7 O O2/5 VIO --- C16 2 MD56 I/O INT, TS2/5 VIO --- C17 2 MD58 I/O INT, TS2/5 VIO --- C18 2 MD60 I/O INT, TS2/5 VIO --- C19 2 MD62 I/O INT, TS2/5 VIO --- C20 GXCLK O O2/5 VIO PMR[29] = 0 and PMR[6] = 1 IRTX O O2/5 PMR[29] = 0 and PMR[6] = 0 TEST3 O O2/5 PMR[29] = 1 and PMR[6] = 1 C21 WR# O O3/5 VIO --- C22 IOW# O O3/5 VIO PMR[21] = x and PMR[2] = 0 DOCW# O (PU22.5) O3/5 PMR[21] = 1 and PMR[2] = 1 GPIO15 I/O (PU22.5) INTS, O8/8 PMR[21] = 0 and PMR[2] = 1 C23 ROMCS# O O3/5 VIO --- BOOT16 I (PD100) INTS VIO Strap C24 VIO PWR --- --- --- C25 GPIO35 I/O (PU22.5) INPCI, OPCI VIO PMR[14] = 0 LAD3 I/O (PU22.5) INPCI, OPCI PMR[14] = 1 C26 GPIO36 I/O (PU22.5) INPCI, OPCI VIO PMR[14] = 0 LDRQ# I (PU22.5) INPCI PMR[14] = 1 D1 SDTEST1 O O2/5 VIO --- D2 MA12 O O2/5 VIO --- D3 CASA# O O2/5 VIO --- D4 SDCLK_IN I INT VIO --- D5 SDTEST3 O O2/5 VIO --- D6 2 MD48 I/O INT, TS2/5 VIO --- D7 2 MD50 I/O INT, TS2/5 VIO --- D8 VIO PWR --- --- --- D9 VSS GND --- --- --- Ball No. Signal Name I/O (PU/PD) Buffer1 Type Power Rail Configuration D10 VIO PWR --- --- --- D11 VSS GND --- --- --- D12 VCORE PWR --- --- --- D13 VSS GND --- --- --- D14 VSS GND --- --- --- D15 VCORE PWR --- --- --- D16 VSS GND --- --- --- D17 VIO PWR --- --- --- D18 VSS GND --- --- --- D19 VIO PWR --- --- --- D20 NC --- --- --- --- D21 GPIO20 I/O (PU22.5) INTS, O8/8 VIO PMR[7] = 0 DOCCS# O O3/5 PMR[7] = 1 D22 GPIO14 I/O PU22.5) INTS, O8/8 VIO PMR[21] = 0 and PMR[2] = 0 IOCS1# O (PU22.5) O3/5 PMR[21] = 0 and PMR[2] = 1 IOR# O O3/5 PMR[21] = 1 and PMR[2] = 0 DOCR# O O3/5 PMR[21] = 1 and PMR[2] = 1 D23 RD# O O3/5 VIO --- CLKSEL0 I (PD100) INTS Strap D24 AD7 I/O INPCI, OPCI VIO Cycle Multiplexed A7 O OPCI D25 GPIO33 I/O (PU22.5) INPCI, OPCI VIO PMR[14] = 0 LAD1 I/O (PU22.5) INPCI, OPCI PMR[14] = 1 D26 GPIO34 I/O (PU22.5) INPCI, OPCI VIO PMR[14] = 0 LAD2 I/O (PU22.5) INPCI, OPCI PMR[14] = 1 E1 2 MD14 I/O INT, TS2/5 VIO --- E2 2 MD15 I/O INT, TS2/5 VIO --- E3 SDTEST4 O O2/5 VIO --- E4 SDCLK0 O O2/5 VIO --- E23 AD8 I/O INPCI, OPCI VIO Cycle Multiplexed A8 O OPCI E24 C/BE0# I/O (PU22.5) INPCI, OPCI VIO Cycle Multiplexed D8 I/O (PU22.5) INPCI, OPCI E25 AD0 I/O INPCI, OPCI VIO Cycle Multiplexed A0 O OPCI Ball No. Signal Name I/O (PU/PD) Buffer1 Type Power Rail Configuration Table 2-2. Ball Assignment - Sorted by Ball Number (Continued) |
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