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SC1100 Datasheet(PDF) 32 Page - National Semiconductor (TI) |
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SC1100 Datasheet(HTML) 32 Page - National Semiconductor (TI) |
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32 / 348 page ![]() www.national.com 32 Revision 1.1 Signal Definitions (Continued) 2.3 MULTIPLEXING CONFIGURATION The tables that follow list multiplexing options and their configurations. Certain multiplexing options may be chosen per signal; others are available only for a group of signals. A pull-up resistor is optional on the balls multiplexed with GPIO11, GPIO16, GPIO40, and GPIO41 regardless of their selected function. For other GPIO pins, the pull-up resistor is optional with regards to the selected function on the relevant ball (see Table 2-2 on page 19 or Table 7-6 on page 285). The pull-up resistor can be disabled by writing Core Logic registers. Table 2-5. Two-Signal/Group Multiplexing Ball No. Default Alternate Signal Configuration Signal Configuration --- Sub-ISA GPIO B22 TRDE# PMR[12] = 0 GPIO0 PMR[12] = 1 Internal Test AD10 FMUL3B PMR[29] = 0 TEST1 PMR[29] = 1 AC11 PLL5B TEST2 --- GPIO LPC E26 GPIO32 PMR[14] = 0 LAD01 PMR[14] = 1 D25 GPIO33 LAD11 D26 GPIO34 LAD21 C25 GPIO35 LAD31 C26 GPIO36 LDRQ#1 B24 GPIO37 LFRAME#1 A24 GPIO39 PMR[16] = 0 SERIRQ1 PMR[16] = 1 --- GPIO PCI Y24 GPIO19 PMR[4] = 0 INTC#2 PMR[4] = 1 --- GPIO Sub-ISA B21 GPIO2 PMR[1] = 0 F5BAR4CS# PMR[1] = 1 A22 GPIO3 PMR[3] = 0 F5BAR5CS# PMR[3] = 1 D21 GPIO20 PMR[7] = 0 DOCCS# PMR[7] = 1 |
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