SC1100 datasheet(96/348 Pages) NSC

96 / 348 page

www.national.com

Revision 1.1

SuperI/O Module (Continued)

CEIR Wakeup Range 1 Registers

These two registers (IRWTR1L and IRWTR1H) define the low and high limits of time range 1 (see Table 4-24 on page 92). The values

are represented in units of 0.1 msec.

•

RC-5 protocol: The pulse width defining a half-bit cell must fall within this range in order for the cell to be considered valid. The

nominal pulse width is 0.889 for a 38 KHz carrier. IRWTR1L and IRWTR1H should be set to 07h and 0Bh, respectively. (Default)

•

NEC protocol: The time between two consecutive CEIR pulses that encodes a bit value of 1 must fall within this range. The nominal

time for a 1 is 2.25 msec for a 36 KHz carrier. IRWTR1L and IRWTR1H should be set to 14h and 19h, respectively.

Bank 1, Offset 0Ah

IRWTR1L Register (R/W)

Reset Value: 07h

This register is set to 07h on power-up of VPP or software reset.

7:5

Reserved.

4:0

CEIR Pulse Change, Range 1, Low Limit.

Bank 1, Offset 0Bh

IRWTR1H Register (R/W)

Reset Value: 0Bh

This register is set to 0Bh on power-up of VPP or software reset.

7:5

Reserved.

4:0

CEIR Pulse Change, Range 1, High Limit.

CEIR Wakeup Range 2 Registers

These two registers (IRWTR2L and IRWTR2H) define the low and high limits of time range 2 (see Table 4-24 on page 92). The values

are represented in units of 0.1 msec.

•

RC-5 protocol: These registers are not used when the RC-5 protocol is selected.

•

NEC protocol: The header pulse width must fall within this range in order for the header to be considered valid. The nominal value is

9 msec for a 38 KHz carrier. IRWTR2L and IRWTR2H should be set to 50h and 64h, respectively. (Default)

Bank 1, Offset 0Ch

IRWTR2L Register (R/W)

Reset Value: 50h

This register is set to 50h on power-up of VPP or software reset.

7:0

CEIR Pulse Change, Range 2, Low Limit.

Bank 1, Offset 0Dh

IRWTR2H Register (R/W)

Reset Value: 64h

This register is set to 64h on power-up of VPP or software reset.

7:0

CEIR Pulse Change, Range 2, High Limit.

CEIR Wakeup Range 3 Registers

These two registers (IRWTR3L and IRWTR3H) define the low and high limits of time range 3 (see Table 4-24 on page 92). The values

are represented in units of 0.1 msec.

•

RC-5 protocol: These registers are not used when the RC-5 protocol is selected.

• NEC protocol: The post header gap width must fall within this range in order for the gap to be considered valid. The nominal value is

4.5 msec for a 36 KHz carrier. IRWTR3L and IRWTR3H should be set to 28h and 32h, respectively. (Default)

Bank 1, Offset 0Eh

IRWTR3L Register (R/W)

Reset Value: 28h

This register is set to 28h on power-up of VPP or software reset.

7:0

CEIR Pulse Change, Range 3, Low Limit.

Bank 1, Offset 0Fh

IRWTR3H Register (R/W)

Reset Value: 32h

This register is set to 32h on power-up of VPP or software reset.

7:0

CEIR Pulse Change, Range 3, High Limit.

Table 4-28. Bank 1 - CEIR Wakeup Configuration and Control Registers (Continued)

Bit

Description

SC1100 Datasheet(PDF) 96 Page - National Semiconductor (TI)

SC1100 Datasheet(HTML) 96 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL