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SC1100 Datasheet(PDF) 63 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # SC1100
Description  Geode??Information Appliance On a Chip
PDF  348 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

SC1100 Datasheet(HTML) 63 Page - National Semiconductor (TI)

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Revision 1.1
63
www.national.com
General Configuration Block (Continued)
3.5.6
Clock Registers
Table 3-8. Clock Generator Configuration
Bit
Description
Offset: 10h
Maximum Core Clock Multiplier Register - MCCM (RO)
Reset Value: Strapped Value
Width: Byte
This register holds the maximum core clock multiplier value. The maximum clock frequency allowed by the core, is the Fast-PCI clock
multiplied by this value.
7:4
Reserved.
3:0
MCM (Maximum Clock Multiplier). This 4-bit value is the maximum multiplier value allowed for the core clock generator. It
is derived from strap options CLKSEL[3:0] (balls AE22, AD22, AD25, D23).
Offset: 12h
PLL Power Control Register - PPCR (R/W)
Reset Value: 2Fh
Width: Byte
This register controls operation of the PLLs.
7
Reserved. Write as read.
6
EXPCID (Disable External PCI Clock).
0: External PCI clock is enabled.
1: External PCI clock is disabled.
5
Reserved. Must be written as 1.
4
Reserved. Write as read.
3
PLL3SD (Shut Down PLL3). AC97 codec clock.
0: PLL3 is enabled.
1: PLL3 is shutdown.
2
FM1SD (Shut Down PLL4).
0: PLL4 is enabled.
1: PLL4 is shutdown.
1
C48MD (Disable SuperI/O and USB Clock).
0: USB and SuperI/O clock is enabled.
1: USB and SuperI/O clock is disabled.
0
Reserved. Write as read.
Offset: 18h
PLL3 Configuration Register - PLL3C (R/W)
Reset Value: E1040005h
Width: DWORD
31:24
MFFC (MFF Counter Value).
FVCO
= OSCCLK * MFBC / (MFFC * MOC)
OSCCLK = 27 MHz
23:19
Reserved. Write as read.
18:8
MFBC (MFB Counter Value).
FVCO
= OSCCLK * MFBC / (MFFC * MOC)
OSCCLK = 27 MHz
7
Reserved. Write as read.
6
Reserved. Must be set to 0.
5:0
MOC (MO Counter Value).
FVCO
= OSCCLK * MFBC / (MFFC * MOC)
OSCCLK = 27 MHz



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