SC1100 datasheet(62/348 Pages) NSC

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Revision 1.1

General Configuration Block (Continued)

3.5.4

SuperI/O Clocks

The SuperI/O module requires a 48 MHz input to the UART

and other functions. This clock is supplied by PLL4 using a

multiplier value of 576/(108x3) to generate 48 MHz.

3.5.5

Core Logic Module Clocks

The Core Logic module requires the following clock

sources:

Real Time (RTC)

RTC requires a 32.768 KHz clock which is supplied directly

from an internal low-power crystal oscillator. This oscillator

uses battery power and has very low current consumption.

USB

The USB requires a 48 MHz input which is supplied by

PLL4. The required total frequency accuracy and slow jitter

for USB is 500 PPM; edge to edge jitter is

±1.2%.

ACPI

The ACPI logic block uses a 14.32 MHz clock supplied by

FMUL3. FMUL3 creates this clock from the 32.768 KHz

clock, with a multiplier value of 6992/4 to output a 57.278

MHz clock that is divided by 4.

External PCI

The PCI Interface uses a 33.3 MHz clock that is created by

PLL5 and divided by 2. PLL5 uses the 27 MHz clock, to

output a 66.67 MHz clock. PLL5 has a frequency accuracy

± 0.1%.

AC97

The SC1100 generates the 24.576 MHz clock required by

the audio codec. Therefore, no crystal need be included for

the audio codec on the system board.

PLL3 uses the crystal oscillator clock to generate a 24.576

MHz clock. This clock is driven on the AC97_CLK signal

(ball AC21). The accuracy of the clock supplied by the

SC1100 is 50 PPM.

Figure 3-4. PLL3 and Dividers Block Diagram

27 MHz

VCO

Phase

Compare

Divide by

MFF

Divide by

MFB

Divide by

SHUTDOWN

Reference Input

VCO clock

PLL3

OUTPUT

SC1100 Datasheet(PDF) 62 Page - National Semiconductor (TI)

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