SC1100 datasheet(61/348 Pages) NSC

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General Configuration Block (Continued)

3.5.2

GX1 Module Core Clock

The core clock is generated by an Analog Delay Loop

(ADL) clock generator from the internal Fast-PCI clock. The

clock can be any whole-number multiple of the input clock

between 4 and 10. Possible values are listed in Table 3-6.

At power-on reset, the core clock multiplier value is set

according to the value of four strapped pins - CLKSEL[3:0]

(balls AE22, AD22, AD25, D23). These pins also select the

clock which is used as input to the multiplier.

3.5.3

Internal Fast-PCI Clock

The internal Fast-PCI clock can be configured to 33 or 66

MHz via strap pins CLKSEL1 and CLKSEL0. These can be

read in the internal Fast-PCI Clock field in the CCFC regis-

ter (GCB+I/O Offset 1Eh[9:8]). (See Table 3-2 on page 50

details on the CCFC register.)

Table 3-6. Core Clock Frequency

ADL

Multiplier

Value

Internal Fast-PCI Clock Freq. (MHz)

33.33

66.67

---

266.7

7233.3

–

8266.7

–

300

–

Table 3-7. Strapped Core Clock Frequency

CLKSEL[3:0]

Straps

Internal Fast-PCI Clock

Freq. (MHz)

(GCB+I/O Offset 1Eh[9:8])

Default ADL Multiplier

Maximum Core

Clock Freq. (MHz)

Multiply By

Multiplier Value

(GCB+I/O Offset 1Eh[3:0])

0000

33.33

0111

233

0100

1000

266

1000

1001

300

0110

66.67

0100

266

SC1100 Datasheet(PDF) 61 Page - National Semiconductor (TI)

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