SC1100 datasheet(98/348 Pages) NSC

98 / 348 page

www.national.com

Revision 1.1

SuperI/O Module (Continued)

4.7.3

Acknowledge (ACK) Cycle

The ACK cycle consists of two signals: the ACK clock

pulse sent by the master with each byte transferred, and

the ACK signal sent by the receiving device (see Figure 4-

15).

The master generates the ACK clock pulse on the ninth

clock pulse of the byte transfer. The transmitter releases

the ABD line (permits it to go high) to allow the receiver to

send the ACK signal. The receiver must pull down the ABD

line during the ACK clock pulse, signalling that it has cor-

rectly received the last data byte and is ready to receive

the next byte. Figure 4-16 illustrates the ACK cycle.

Figure 4-15. ACCESS.bus Data Transaction

Figure 4-16. ACCESS.bus Acknowledge Cycle

Start

Condition

Stop

Condition

ABD

ABC

MSB

ACK

12 3 - 6

23 - 8

Acknowledge

Signal From Receiver

Byte Complete

Interrupt Within

Receiver

Clock Line Held

Low by Receiver

While Interrupt

is Serviced

Start

Condition

ABC

12 3 - 6

Transmitter Stays Off Bus

During Acknowledge Clock

Acknowledge

Signal From Receiver

Data Output

by Transmitter

Data Output

by Receiver

SC1100 Datasheet(PDF) 98 Page - National Semiconductor (TI)

SC1100 Datasheet(HTML) 98 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL