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SC1100 Datasheet(PDF) 37 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # SC1100
Description  Geode??Information Appliance On a Chip
PDF  348 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

SC1100 Datasheet(HTML) 37 Page - National Semiconductor (TI)

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Revision 1.1
37
www.national.com
Signal Definitions (Continued)
PCIRST#
M26
O
PCI and System Reset. PCIRST# is the reset signal for
the PCI bus and system. It is asserted for approximately
100 µs after POR# is negated.
---
2.4.2
Memory Interface Signals
Signal Name
Ball No.
Type
Description
Mux
MD[63:0]
See
Table 2-3
on page
27
I/O
Memory Data Bus. The data bus lines driven to/from
system memory.
---
MA[12:0]
See
Table 2-3
on page
27
O
Memory Address Bus. The multiplexed row/column
address lines driven to the system memory. Supports
256-Mbit SDRAM.
---
BA1
C12
O
Bank Address Bits. These bits are used to select the
component bank within the SDRAM.
---
BA0
C11
---
CS1#
A3
O
Chip Selects. These bits are used to select the module
bank within system memory. Each chip select corre-
sponds to a specific module bank. If CS# is high, the
bank(s) do not respond to RAS#, CAS#, and WE# until
the bank is selected again.
---
CS0#
B3
---
RASA#
C1
O
Row Address Strobe. RAS#, CAS#, WE# and CKE are
encoded to support the different SDRAM commands.
RASA# is used with CS[1:0]#.
---
CASA#
D3
O
Column Address Strobe. RAS#, CAS#, WE# and CKE
are encoded to support the different SDRAM commands.
CASA# is used with CS[1:0]#.
---
WEA#
C2
O
Write Enable. RAS#, CAS#, WE# and CKE are encoded
to support the different SDRAM commands. WEA# is
used with CS[1:0]#.
---
DQM[7:0]
C15,
C14, N3,
P3, A11,
B11, M2,
M1
O
Data Mask Control Bits. During memory read cycles,
these outputs control whether SDRAM output buffers are
driven on the MD bus or not. All DQM signals are
asserted during read cycles.
During memory write cycles, these outputs control
whether or not MD data is written into SDRAM.
DQM[7:0] connect directly to the [DQM7:0] pins of each
DIMM connector.
---
CKEA
A19
O
Clock Enable. These signals are used to enter Sus-
pend/power-down mode. CKEA is used with CS[1:0]#.
If CKE goes low when no read or write cycle is in
progress, the SDRAM enters power-down mode. To
ensure that SDRAM data remains valid, the self-refresh
command is executed. To exit this mode, and return to
normal operation, drive CKE high.
These signals should have an external pull-down resistor
of 33 K
Ω.
---
2.4.1
System Interface (Continued)
Signal Name
Ball No.
Type
Description
Mux



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