SC1100 datasheet(14/348 Pages) NSC

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Revision 1.1

Architecture Overview (Continued)

1.2

CORE LOGIC MODULE

The Core Logic module is described in detail in Section 5.0

"Core Logic Module" on page 116.

The Core Logic module is connected to the Fast-PCI bus. It

uses signal AD28 as the IDSEL for all PCI configuration

functions except for USB which uses AD29.

1.2.1

Other Interfaces of the Core Logic Module

All the following interfaces of the Core Logic module are

implemented via external pins of the SC1100. Each inter-

face is listed below with a reference to the descriptions of

the relevant pins.

• IDE: See Section 2.4.7 "IDE Interface Signals" on page

42.

• AC97: See Section 2.4.10 "AC97 Audio Interface

Signals" on page 44.

• PCI: See Section 2.4.4 "PCI Bus Interface Signals" on

page 38.

• USB: See Section 2.4.8 "Universal Serial Bus (USB)

Interface Signals" on page 43. The USB function uses

signal AD29 as the IDSEL for PCI configuration.

• LPC: See Section 2.4.6 "Low Pin Count (LPC) Bus Inter-

face Signals" on page 42.

• Sub-ISA: See Section 2.4.5 "Sub-ISA Interface Signals"

on page 41, Section 5.2.5 "Sub-ISA Bus Interface" on

page 122, and Section 3.2 "Multiplexing, Interrupt Selec-

tion, and Base Address Registers" on page 50.

• GPIO: See Section 2.4.12 "GPIO Interface Signals" on

page 45.

• More detailed information about each of these interfaces

is provided in Section 5.2 "Module Architecture and

Configuration" on page 117.

• Super/IO Block Interfaces: See Section 3.2 "Multi-

plexing, Interrupt Selection, and Base Address Regis-

ters" on page 50, Section 2.4.3 "ACCESS.bus Interface

Signals" on page 38, Section 2.4.9 "Serial Port (UART)

and Infrared (IR) Interface Signals" on page 43.

The Core Logic module interface to the GX1 module con-

sists of seven miscellaneous connections, and the Fast-

PCI bus interface signals. Note that the PC/AT legacy pins

NMI, WM_RST, and A20M are all virtual functions exe-

cuted in SMM (System Management Mode) by the BIOS.

• PSERIAL is a one-way serial bus from the GX1 to the

Core Logic module used to communicate power

management states.

• IRQ13 is an input from the processor indicating that a

floating point error was detected and that INTR should

be asserted.

• INTR is the level output from the integrated 8259A PICs

and is asserted if an unmasked interrupt request (IRQn)

is sampled active.

• SMI# is a level-sensitive interrupt to the GX1 that can be

configured to assert on a number of different system

events. After an SMI# assertion, SMM is entered and

program execution begins at the base of the SMM

address space. Once asserted, SMI# remains active

until the SMI source is cleared.

• SUSP# and SUSPA# are handshake pins for imple-

menting GX1 module Clock Stop and clock throttling.

• CPU_RST resets the GX1 module and is asserted for

approximately 100 µs after the negation of POR#.

• Fast-PCI bus interface signals.

1.3

SUPERI/O MODULE

The SuperI/O (SIO) module is a member of National Semi-

conductor’s SuperI/O family of integrated PC peripherals. It

is a PC98 and ACPI compliant SIO that offers a single-cell

solution to the most commonly used ISA peripherals.

The SIO module incorporates: a Serial Port, an Infrared

Communication Port that supports FIR, MIR, HP-SIR,

Sharp-IR, and Consumer Electronics-IR, two ACCESS.bus

Interface (ACB) ports, System Wakeup Control (SWC), and

a Real-Time Clock (RTC) that provides RTC timekeeping.

1.4

CLOCK, TIMERS, AND RESET LOGIC

In addition to the three main modules (i.e., GX1, Core

Logic, and SIO) that make up the SC1100, the following

blocks of logic have also been integrated into the SC1100:

• Clock Generators as described in Section 3.5 "Clock

Generators and PLLs" on page 59.

• Configuration Registers as described in Section 3.2

"Multiplexing, Interrupt Selection, and Base Address

Registers" on page 50.

• A WATCHDOG timer as described in Section 3.3

"WATCHDOG" on page 55.

• A High Resolution timer as described in Section 3.4

"High-Resolution Timer" on page 57.

1.4.1

Reset Logic

This section provides a description of the reset flow of the

SC1100.

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