SC1100 datasheet(38/348 Pages) NSC

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Revision 1.1

Signal Definitions (Continued)

SDCLK3

A17

SDRAM Clocks. SDRAM uses these clocks to sample

all control, address, and data lines. To ensure that the

Suspend mode functions correctly, SDCLK3 and

SDCLK1 should be used with CS1#. SDCLK2 and

SDCLK0 should be used together with CS0#.

---

SDCLK2

A16

---

SDCLK1

---

SDCLK0

---

SDCLK_IN

SDRAM Clock Input. The SC1100 samples the memory

read data on this clock. Works in conjunction with the

SDCLK_OUT signal.

---

SDCLK_OUT

SDRAM Clock Output. This output is routed back to

SDCLK_IN. The board designer should vary the length of

the board trace to control skew between SDCLK_IN and

SDCLK.

---

2.4.3

ACCESS.bus Interface Signals

Signal Name

Ball No.

Type

Description

Mux

AB1C

I/O

ACCESS.bus 1 Serial Clock. This is the serial clock for

the interface.

F_AD1

AB1D

I/O

ACCESS.bus 1 Serial Data. This is the bidirectional

serial data signal for the interface.

F_AD2

AB2C

AE23

I/O

ACCESS.bus 2 Serial Clock. This is the serial clock for

the interface.

GPIO12+F_AD3

AB2D

AD23

I/O

ACCESS.bus 2 Serial Data. This is the bidirectional

serial data signal for the interface.

GPIO13+F_AD4

2.4.4

PCI Bus Interface Signals

Signal Name

Ball No.

Type

Description

Mux

PCICLK

AA23

PCI Clock. PCICLK provides timing for all transactions

on the PCI bus. All other PCI signals are sampled on the

rising edge of PCICLK, and all timing parameters are

defined with respect to this edge.

---

PCICLKO

AB25

PCI Clock Output. Provides a clock for the system at 33

MHz. This clock is asynchronous to PCI signals. It should

be connected to a low skew buffer with multiple outputs,

of which one is connected to the PCICLK input. All PCI

clock users in the system (including PCICLK) should

receive the clock with as low a skew as possible.

Note:

Only a CMOS load should be connected to this

signal.

FPCI_MON

(Strap)

AD[31:24]

See

Table 2-3

on page

I/O

Multiplexed Address and Data. A bus transaction con-

sists of an address phase in the cycle in which FRAME#

is asserted followed by one or more data phases. During

the address phase, AD[31:0] contain a physical 32-bit

address. For I/O, this is a byte address. For configuration

and memory, it is a DWORD address. During data

phases, AD[7:0] contain the least significant byte (LSB)

and AD[31:24] contain the most significant byte (MSB).

D[7:0]

AD[23:0]

A[23:0]

2.4.2

Memory Interface Signals (Continued)

Signal Name

Ball No.

Type

Description

Mux

SC1100 Datasheet(PDF) 38 Page - National Semiconductor (TI)

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