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SC1100 Datasheet(PDF) 64 Page - National Semiconductor (TI) |
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SC1100 Datasheet(HTML) 64 Page - National Semiconductor (TI) |
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64 / 348 page  www.national.com 64 Revision 1.1 General Configuration Block (Continued) Offset: 1Eh Core Clock Frequency Control Register - CCFC (R/W) Reset Value: Strapped Value Width: WORD This register controls the configuration of the core clock multiplier and the reference clocks. 15:14 Reserved. Write as read. 13 Reserved. Must be cleared to 0. 12 Reserved. Must be cleared to 0. 11:10 Reserved. Write as read. 9:8 FPCICK (Internal Fast-PCI Clock). (Read Only) Reflects the internal Fast-PCI clock and is the input to the GX1 module that is used to generate the core clock. These bits reflect the value of strap pins CLKSEL[1:0] (balls D23, AD25). 00: 33.3 MHz 01: Reserved 10: 66.7 MHz 11: 33.3 MHz 7:4 Reserved. Write as read. 3:0 MVAL (Multiplier Value). This 4-bit value controls the multiplier in ADL. The value is set according to the Maximum Clock Multiplier bits of the MCCM register (Offset 10h). The multiplier value should never be written with a multiplier which is differ- ent from the multiplier indicated in the MCCM register. 0100: Multiply by 4 0111: Multiply by 7 1000: Multiply by 8 Other: Reserved Table 3-8. Clock Generator Configuration (Continued) Bit Description |
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