SC1100 datasheet(42/348 Pages) NSC

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Revision 1.1

Signal Definitions (Continued)

2.4.6

Low Pin Count (LPC) Bus Interface Signals

Signal Name

Ball No.

Type

Description

Mux

LAD[3:0]

C25,

D26,

D25, E26

I/O

LPC Address-Data. Multiplexed command, address,

bidirectional data, and cycle status.

GPIO[35:32]

LDRQ#

C26

LPC DMA Request. Encoded DMA request for LPC

interface.

GPIO36

LFRAME#

B24

LPC Frame. A low pulse indicates the beginning of a

new LPC cycle or termination of a broken cycle.

GPIO37

SERIRQ

A24

I/O

Serial IRQ. The interrupt requests are serialized over a

single signal, where each IRQ level is delivered during a

designated time slot.

GPIO39

2.4.7

IDE Interface Signals

Signal Name

Ball No.

Type

Description

Mux

IDE_RST#

AD6

IDE Reset. This signal resets all the devices that are

attached to the IDE interface.

---

IDE_ADDR[2:0]

Y3, AA3,

AA4

IDE Address Bits. These address bits are used to

access a register or data port in a device on the IDE bus.

---

IDE_DATA[15:0]

See

Table 2-3

on page

I/O

IDE Data Lines. IDE_DATA[15:0] transfers data to/from

the IDE devices.

---

IDE_IOR0#

AC1

IDE I/O Read Channels 0 and 1. IDE_IOR0# is the read

signal for Channel 0 and IDE_IOR1# is the read signal

for Channel 1. Each signal is asserted at read accesses

to the corresponding IDE port addresses.

---

IDE_IOR1#

AD12

GPIO6+DTR#/

BOUT+INTR_O

IDE_IOW0#

AC2

IDE I/O Write Channels 0 and 1. IDE_IOW0# is the

write signal for Channel 0. IDE_IOW1# is the write signal

for Channel 1. Each signal is asserted at write accesses

to corresponding IDE port addresses.

---

IDE_IOW1#

AE12

GPIO9+DCD#+F

_IRDY#

IDE_CS0#

AA2

IDE Chip Selects 0 and 1. These signals are used to

select the command block registers in an IDE device.

---

IDE_CS1#

AA1

---

IDE_IORDY0

AB2

I/O Ready Channels 0 and 1. When deasserted, these

signals extend the transfer cycle of any host register

access if the required device is not ready to respond to

the data transfer request.

---

IDE_IORDY1

AF12

GPIO10+DSR#+

F_FRAME#

IDE_DREQ0

AB3

DMA Request Channels 0 and 1. The IDE_DREQ sig-

nals are used to request a DMA transfer from the

SC1100. The direction of transfer is determined by the

IDE_IOR#/IOW# signals.

---

IDE_DREQ1

AC12

GPIO8+CTS#

+SMI_O

IDE_DACK0#

AB1

DMA Acknowledge Channels 0 and 1. The

IDE_DACK# signals acknowledge the DREQ request to

initiate DMA transfers.

---

IDE_DACK1#

AF11

GPIO7+RTS#

F_C/BE3#

IRQ14

AC6

Interrupt Request Channels 0 and 1. These input sig-

nals are edge-sensitive interrupts that indicate when the

IDE device is requesting a CPU interrupt service.

---

IRQ15

AF19

GPIO11+RI#

SC1100 Datasheet(PDF) 42 Page - National Semiconductor (TI)

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