SC1100 datasheet(12/348 Pages) NSC

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Revision 1.1

Architecture Overview (Continued)

1.1.6

Integrated Functions

The GX1 module integrates the following functions tradi-

tionally implemented using external devices:

• SDRAM memory controller

• PCI bridge

The module has also been enhanced to support VSA tech-

nology implementation.

1.1.6.1

Memory Subsystem

The memory controller drives a 64-bit SDRAM port directly.

Up to two module banks of SDRAM are supported. Each

module bank can have two or four component banks

depending on the memory size and organization. The max-

imum configuration is two module banks with four compo-

nent banks, each providing a total of 16 open banks. The

maximum memory size is 512 MB.

The memory controller handles multiple requests for mem-

ory data from the GX1 module, and other sources via Fast-

PCI. The memory controller contains extensive buffering

logic that helps minimize contention for memory band-

width. The memory controller cooperates with the internal

bus controller to determine the cacheability of all memory

references.

1.1.6.2

PCI Controller

The GX1 module incorporates a full-function PCI interface

module that includes the PCI arbiter. All accesses to exter-

nal I/O devices are sent over the Fast-PCI bus, although

most memory accesses are serviced by the SDRAM con-

troller. The internal bus interface unit contains address

mapping logic that determines if memory accesses are tar-

geted for the SDRAM or for the PCI bus. The PCI bus in an

SC1100- based system is 3.3 volt only. Do not connect 5

volt devices on this bus.

1.1.6.3

Fast-PCI Bus

The GX1 module communicates with the Core Logic mod-

ule via a Fast-PCI bus that can work at up to 66 MHz. The

Fast-PCI bus is internal for the SC1100 and is connected

to the Configuration Block.

1.1.7

Differences from Standalone GX1

1.1.7.1

Device ID

The SC1100’s device ID is contained within the GX1 mod-

ule. Software can detect the revision by reading the DIR0

and DIR1 Configuration registers (see Configuration regis-

ters in the Geode GX1 Processor Series datasheet). The

SC1100 device errata contains the specific values.

1.1.7.2

SDRAM

The GX1 module is connected to external SDRAM DIMMs.

For more information see Section 2.4.2 "Memory Interface

Signals" on page 37, and the “Memory Controller” chapter

in the GX1 Processor Series datasheet. The drive

strength/slew control in the memory controller block (see

Table 1-1) is different from the standalone GX1 processor.

Table 1-1. SC1100 GX1 Module System Memory Buffer Strength Control

Bit

Description

GX_BASE+Memory Offset 8400h

MC_MEM_CNTRL1 (R/W)

Reset Value: 248C0040h

Width: DWORD

31:30

MD[63:0] Drive Strength: 11 is strongest, 00 is weakest.

28:27

MA[12:0] and BA[1:0] Drive Strength: 11 is strongest, 00 is weakest.

25:24

RASA#, CASA#, WEA#, CS[1:0]#, CKEA, DQM[7:0] Drive Strength: 11 is strongest, 00 is weakest.

X-Bus Round Robin. Must be written with 1.

GX_BASE+Memory Offset 8404h

MC_MEM_CNTRL2 (R/W)

Reset Value: 00000801h

Width: DWORD

13:12

SCLK High Drive/Slew Control: Controls the high drive and slew rate of SDCLK[3:0] and SDCLK_OUT.

11 is strongest, 00 is weakest.

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