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Signal Definitions (Continued)

The remaining subsections of this chapter describe:

• Section 2.1 "Ball Assignments": Provides a ball assign-

ment diagram and tables listing the signals sorted

according to ball number and alphabetically by signal

name.

• Section 2.2 "Strap Options": Several balls are read at

power-up that set up the state of the SC1100. This

section provides details regarding those balls.

• Section 2.3 "Multiplexing Configuration": Lists multi-

plexing options and their configurations.

• Section 2.4 "Signal Descriptions": Detailed descriptions

of each signal according to functional group.

2.1

BALL ASSIGNMENTS

The SC1100 is configurable. Strap options and register

programming are used to set various modes of operation

and specific signals on specific balls. This section

describes which signals are available on which balls and

provides configuration information:

• Figure 2-2 "388-Terminal Ball Assignment Diagram (Top

View)" on page 18: Illustration of ball assignment.

• Table 2-2 "Ball Assignment - Sorted by Ball Number" on

page 19: Lists signals according to ball number. Power

Rail, Signal Type, Buffer Type and, where relevant, Pull-

Up or Pull-Down resistors are indicated for each ball in

this table. For multiplexed balls, the necessary configu-

ration for each signal is listed as well.

• Table 2-3 "Ball Assignment - Sorted Alphabetically by

Signal Name" on page 27: Quick reference list sorted

alphabetically listing all signal names.

The tables in this chapter use several common abbrevia-

tions. Table 2-1 lists the mnemonics and their meanings.

Notes:

For each GPIO signal, there is an optional pull-up

resistor on the relevant ball. After system reset, the

pull-up is present.

This pull-up resistor can be disabled via registers in the

Core Logic module. The configuration is without regard

to the selected ball function (except for GPIO12,

GPIO13, and GPIO16). Alternate functions for GPIO12,

GPIO13, and GPIO16 control pull-up resistors.

For more information, see Section 5.4.1 "Bridge,

GPIO, and LPC Registers - Function 0" on page 166.

Configuration settings listed in Table 2-2 are with

regard to the Pin Multiplexing Register (PMR). See

Section 3.2 "Multiplexing, Interrupt Selection, and

Base Address Registers" on page 50 for a detailed

description of this register.

Table 2-1. Signal Definitions Legend

Mnemonic

Definition

Analog

AVSS

Ground ball: Analog

AVDD

Power ball: Analog

GCB

General Configuration Block registers.

Refer to Section 3.0 "General Configura-

tion Block" on page 49.

Location of the General Configuration

Block cannot be determined by soft-

ware. See SC1100 Information Appli-

ance On a Chip device errata.

Input ball

I/O

Bidirectional ball

MCR[x]

Miscellaneous Configuration Register

Bit x: A register, located in the GCB.

Refer to Section 3.1 "Configuration

Block Addresses" on page 49 for further

details.

Output ball

Open-drain

Pull-down

PMR[x]

Pin Multiplexing Register Bit x: A regis-

ter, located in the GCB, used to config-

ure balls with multiple functions. Refer to

Section 3.1 "Configuration Block

Addresses" on page 49 for further

details.

Pull-up

TRI-STATE

VCORE

Power ball: 1.8V or 2.0V (speed grade

dependent)

VIO

Power ball: 3.3V

VSS

Ground ball

The # symbol in a signal name indicates

that the active or asserted state occurs

when the signal is at a low voltage level.

Otherwise, the signal is asserted when

at a high voltage level.

A / in a signal name indicates both func-

tions are always enabled (i.e., cycle mul-

tiplexed).

A + in signal name indicates the function

is available on the ball, but that either

strapping options or register program-

ming is required to select the desired

function.

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