SC1100 datasheet(31/348 Pages) NSC

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Signal Definitions (Continued)

2.2

STRAP OPTIONS

Several balls are read at power-up that set up the state of

the SC1100. These balls are typically multiplexed with

other functions that are outputs after the power-up

sequence is complete. The SC1100 must read the state of

the balls at power-up and the internal PU or PD resistors

do not guarantee the correct state will be read. Therefore, it

is required that an external PU or PD resistor with a value

of 1.5 K

Ω be placed on the balls listed in Table 2-4. The

value of the resistor is important to ensure that the proper

state is read during the power-up sequence. If the ball is

not read correctly at power-up, the SC1100 may default to

a state that causes it to function improperly, possibly result-

ing in application failure.

Table 2-4. Strap Options

Strap Option

Muxed With

Ball #

Nominal

Internal

PU or PD

External PU/PD Strap Settings

Strap = 0 (PD)

Strap = 1 (PU)

CLKSEL0

RD#

D23

PD100

See Section 2.4.1 on page 36 for CLK-

SEL strap options.

GCB+I/O Offset 1Eh[9:8] (RO):

Value programmed at reset by

CLKSEL[1:0].

GCB+I/O Offset 10h[3:0] (RO):

Value programmed at reset by

CLKSEL[3:0].

GCB+I/O Offset 1Eh[3:0] (R/W, but

write not recommended): Value pro-

grammed at reset by CLKSEL[3:0].

Note: Values for GCB+I/O Offset

10h[3:0] and 1Eh[3:0] are not the

same.

CLKSEL1

GNT1#

AD25

PD100

CLKSEL2

SDATA_OUT

AD22

PD100

CLKSEL3

SYNC

AE22

PD100

BOOT16

ROMCS#

C23

PD100

Enable boot from

8-bit ROM

Enable boot from

16-bit ROM

GCB+I/O Offset 34h[3] (RO): Reads

back strap setting.

GCB+I/O Offset 34h[14] (R/W):

Used to allow the ROMCS# width to

be changed under program control.

FPCI_MON

PCICLKO

AB25

PD100

Disable Fast-PCI,

INTR_O, and

SMI_O monitor-

ing signals.

Enable Fast-PCI,

INTR_O, and

SMI_O monitor-

ing signals. (Use-

ful during debug.)

GCB+I/O Offset 34h[30] (MCR[30])

(RO): Reads back strap setting.

Note: For normal operation, strap

this signal low using a 1.5 K

Ω

resistor.

LPC_ROM

GNT0#

AB26

PD100

Disable LPC

ROM boot

Enable boot from

LPC ROM device

This strap signal, when pulled high,

sets bit F0BAR1+I/O Offset 10h[15],

LPC ROM Addressing Enable.

Note: Accuracy of internal PU/PD resistors: 80K to 250K.

Location of the GCB (General Configuration Block) cannot be determined by software. See the SC1100 Information Appliance On

a Chip device errata document.

SC1100 Datasheet(PDF) 31 Page - National Semiconductor (TI)

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