SC1100 datasheet(40/348 Pages) NSC

40 / 348 page

www.national.com

Revision 1.1

Signal Definitions (Continued)

STOP#

M25

I/O

Target Stop. STOP# is asserted to indicate that the cur-

rent target is requesting that the master stop the current

transaction. This signal is used with DEVSEL# to indicate

retry, disconnect, or target abort. If STOP# is sampled

active by the master, FRAME# is deasserted and the

cycle is stopped within three PCI clock cycles. As an

input, STOP# can be asserted in the following cases:

If the PCI write buffers are full or if a previously buff-

ered cycle has not completed.

On read cycles that cross cache line boundaries.

This is conditional based upon the programming of

GX1 module’s PCI Configuration Register, Index

41h[1].

D15

DEVSEL#

N26

I/O

Device Select. DEVSEL# indicates that the driving

device has decoded its address as the target of the cur-

rent access. As an input, DEVSEL# indicates whether

any device on the bus has been selected. DEVSEL# is

also driven by any agent that has the ability to accept

cycles on a subtractive decode basis. As a master, if no

DEVSEL# is detected within and up to the subtractive

decode clock, a master abort cycle is initiated (except for

special cycles which do not expect a DEVSEL#

returned).

BHE#

PERR#

J24

I/O

Parity Error. PERR# is used for reporting data parity

errors during all PCI transactions except a Special Cycle.

The PERR# line is driven two PCI clocks after the data in

which the error was detected. This is one PCI clock after

the PAR that is attached to the data. The minimum dura-

tion of PERR# is one PCI clock for each data phase in

which a data parity error is detected. PERR# must be

driven high for one PCI clock before being placed in TRI-

STATE. A target asserts PERR# on write cycles if it has

claimed the cycle with DEVSEL#. The master asserts

PERR# on read cycles.

---

SERR#

L25

I/O

System Error. SERR# can be asserted by any agent for

reporting errors other than PCI parity, so that the PCI

central agent notifies the processor. When the Parity

Enable bit is set in the Memory Controller Configuration

error in read operations from DRAM.

---

REQ3#

T24

Request Lines. Indicates to the arbiter that an agent

requires the bus. Each master has its own REQ# line.

REQ# priorities are based on the specified arbitration

scheme.

---

REQ2#

AC26

---

REQ1#

AA25

---

REQ0#

AA26

---

GNT3#

AC25

Grant Lines. Indicate to the requesting master that it has

been granted access to the bus. Each master has its own

GNT# line. GNT# can be retracted at any time a higher

REQ# is received or if the master does not begin a cycle

within a minimum period of time (16 PCI clocks).

---

GNT2#

U24

---

GNT1#

AD25

CLKSEL1 (Strap)

GNT0#

AB26

LPC_ROM

(Strap)

2.4.4

PCI Bus Interface Signals (Continued)

Signal Name

Ball No.

Type

Description

Mux

SC1100 Datasheet(PDF) 40 Page - National Semiconductor (TI)

SC1100 Datasheet(HTML) 40 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL