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SC1100 Datasheet(PDF) 36 Page - National Semiconductor (TI) |
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SC1100 Datasheet(HTML) 36 Page - National Semiconductor (TI) |
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36 / 348 page  www.national.com 36 Revision 1.1 Signal Definitions (Continued) 2.4 SIGNAL DESCRIPTIONS Information in the tables that follow may have duplicate information in multiple tables. Multiple references all contain identi- cal information. 2.4.1 System Interface Signal Name Ball No. Type Description Mux CLKSEL1 AD25 I Fast-PCI Clock Selects. These strap signals are used to set the internal Fast-PCI clock. 00 = 33.3 MHz 01 = Reserved 10 = 66.7 MHz 11 = 33.3 MHz During system reset, an internal pull-down resistor of 100 K Ω exists on these balls. An external pull-up or pull-down resistor of 1.5 K Ω must be used. GNT1# CLKSEL0 D23 RD# CLKSEL3 AE22 I Maximum Core Clock Multiplier. These strap signals are used to set the maximum allowed multiplier value for the core clock. During system reset, an internal pull-down resistor of 100 K Ω exists on these balls. An external pull-up or pull-down resistor of 1.5 K Ω must be used. SYNC CLKSEL2 AD22 SDATA_OUT BOOT16 C23 I Boot ROM is 16 Bits Wide. This strap signal enables the optional 16-bit wide Sub-ISA bus. During system reset, an internal pull-down resistor of 100 K Ω exists on these balls. An external pull-up or pull-down resistor of 1.5 K Ω must be used. ROMCS# LPC_ROM AB26 I LPC_ROM. If pulled high during reset, this strap signal forces selection of the LPC bus and sets bit F0BAR1+I/O Offset 10h[15], LPC ROM Addressing Enable. It enables the SC1100 to boot from a ROM connected to the LPC bus. During system reset, an internal pull-down resistor of 100 K Ω exists on these balls. An external pull-up or pull-down resistor of 1.5 K Ω must be used. GNT0# FPCI_MON AB25 I Fast-PCI Monitoring. The strap on this ball forces selec- tion of Fast-PCI monitoring signals. For normal operation, strap this signal low using a 1.5 K Ω resistor. The value of this strap can be read on the MCR[30]. PCICLKO POR# AE21 I Power On Reset. POR# is the system reset signal gen- erated from the power supply to indicate that the system should be reset. --- X32I W1 I Crystal Connections. Connected directly to a 32.768 KHz crystal. This clock input is required even if the inter- nal RTC is not being used. Some of the internal clocks are derived from this clock. If an external clock is used, it should be connected to X32I, using a voltage level of 0V to VCORE +10% maximum. X32O should remain uncon- nected. --- X32O W2 O --- X27I AF10 I Crystal Connections. Connected directly to a 27.000 MHz crystal. Some of the internal clocks are derived from this clock. If an external clock is used, it should be con- nected to X27I, using a voltage level of 0V to VIO and X27O should be remain unconnected. --- X27O AE10 O --- |
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