S5335 datasheet(112/189 Pages) AMCC

112 / 189 page

S5335 – PCI Bus Controller, 3.3V

Revision 5.01 – November 30, 2005

AMCC Confidential and Proprietary

DS1657

112

Data Sheet

Asserting PTADR# is functionally identical to access-

ing the Pass-Thru address register with RD#,

SELECT#, BE[3:0]#, and ADR[6:2]. RD# and WR#

must be deasserted when PTADR# is asserted, but

SELECT# may be asserted. These inputs automati-

cally drive the address (internally) to 28h and assert all

byte enables. The ADR[6:2] and BE[3:0]# are ignored

when using the PTADR# direct access input. When

PTADR# is asserted, the contents of the APTA register

are immediately driven onto the Add-On data bus.

The PTADR# direct access signal accesses the Pass-

Thru address register as 16-bits or 32-bits, whatever

the MODE pin is configured for. For 16-bit mode,

PTADR# only presents the lower 16-bits of the APTA

PTRDY# indicates that the Add-On has completed the

current Pass-Thru access. Multiple Add-On reads or

writes may occur to the Pass-Thru data (APTD) regis-

ter before asserting PTRDY#. This may be required for

8-bit or 16-bit Add-On interfaces using multiple

accesses to the 32-bit Pass-Thru data register. In

some cases, the Add-On bus may be 32-bits, but logic

may require multiple BPCLK periods to read or write

data. In this situation, accesses may be extended by

holding off PTRDY#. PTRDY# must be synchronized

to BPCLK.

NON-VOLATILE MEMORY INTERFACE

The S5335 allows read and write access to the nv

memory device used for configuration. Reads are nec-

essary during device initialization as configuration

information is downloaded into the S5335. If an expan-

sion BIOS is implemented in the nv memory, the host

transfers (shadows) the code into system DRAM.

Writes are useful for in-field updates to expansion

BIOS code. This allows software to update the nv

memory contents without altering hardware.

Non-Volatile Memory Interface Signals

For serial nv memory devices, there are only two sig-

nals used to interface with nv memory. SCL is the

serial clock, and SDA is the serial data line. The func-

tionality of these signals is described in-detail in the

PIN description Section of this book. The designer

does not need to generate the timings for SCL and

SDA. The S5335 automatically performs the correct

serial access when programmed for serial devices.

For byte-wide nv memory devices, there is an 8-bit

data bus (EQ7:0), and a 16-bit address bus (EA15:0)

dedicated for the nv memory interface. When a serial

nv memory is implemented, many of these pins have

alternate functions. The S5335 also has read (ERD#)

and write (EWR#) outputs to drive the OE# and WR#

inputs on a byte-wide nv memory. The designer does

not need to generate the timings for these outputs.

The S5335 automatically performs the read and write

accesses when programmed for byte wide devices.

Accessing Non-Volatile Memory

The nv memory, if implemented, can be accessed

through the PCI interface or the Add-On interface.

Accesses from both the PCI side and the Add-On side

must be synchronous with the PCI clock (BPCLK for

the Add-On). Accesses to the nv memory from the PCI

interface are through the Bus Master Control/Status

Accesses to the nv memory from the Add-On interface

are through the Add-On General Control/Status Regis-

ter (AGCSTS) Add-On Operation Register. Accesses

to the MCSR register are from the PCI bus and are,

therefore, automatically synchronous to the PCI clock.

Accesses to the AGCSTS register from the Add-On

S5335 Datasheet(PDF) 112 Page - Applied Micro Circuits Corporation

S5335 Datasheet(HTML) 112 Page - Applied Micro Circuits Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL