S5335 datasheet(113/189 Pages) AMCC

113 / 189 page

S5335 – PCI Bus Controller, 3.3V

Revision 5.01 – November 30, 2005

AMCC Confidential and Proprietary

DS1657

113

Data Sheet

Some nv memories may contain Expansion ROM

BIOS code for use by the host software. During initial-

ization, the Expansion BIOS is located within system

memory. The starting location of the nv memory is

stored in the Expansion ROM Base Address Register

in the S5335 PCI Configuration Registers. A PCI read

from this region results in the S5335 performing four

consecutive byte access to the nv memory device.

Writes to the nv memory are not allowed by writing to

this region. Writes to the nv memory must be per-

formed as described below.

The S5335 contains two latches within the MCSR reg-

ister to control and access the NVRAM. One is an 8 bit

latch called the NVRAM Address/Data Register which

is used to hold NVRAM address and data information.

The other is a 3 bit latch called the NVRAM Access

Control Register which is used to direct the address

and data information and to control the NVRAM itself.

Reading or writing to the NVRAM is performed through

bits D31:29 of this register. These bits are enable and

decode controls rather than a command or instruction

to be executed. D31 of this register is the primary

enable bit which allows all accesses to occur. When

written to a ‘1’, D31 enables the decode bits D30 and

D29 to direct the data contained in the address/data

latch, D23:16, to the low address, high address or data

latches. D31 should be thought of as “opening a door”

where as long as D31 = 1, then the door is open for

address or data information to be altered. The table on

page 5-16 of the S5335 data book shows the D31:29

bit combinations for reading, writing, and loading ad-

dress/data information. Additionally, D31 doubles as

an S5335 status bit. A ‘1’ indicates that the S5335 is

currently busy reading or writing to the NVRAM. A ‘0’

indicates a complete or inactive state.

For the examples below, we will assume the S5335 is

I/O mapped with a base address of FC00h. These

examples will read one byte of the Vendor ID and write

one byte to the Vendor ID.

This example will write 1 byte from NVRAM location 0040h and read it back:

Out

FC00h + 3Fh (offset of NVRAM Access Control Register) until D31 = 0 (not busy).

FC00h + 3FH an 80h (CMD to load the low address byte). This sets decode bits and opens door for low address

latch.

FC00h + 3Eh (offset of Address/Data Register) 40h (the low byte of the address desired) 40h goes into latch but is

not latched yet.

FC00h + 3Fh an A0h (CMD to load the high address byte). This latches the low address through changing the

decode bits and opens the door for the high address latch.

FC00h + 3Eh a 00h (the high byte of the address desired). 00h goes into the latch but is not latched yet.

FC00h + 3Fh an 00h (inactive CMD). This latches the high address through the disabling D31, ‘closes the door’.

FC00h + 3Eh DATA (the data byte to be written). DATA byte goes into the latch but is not latched yet.

FC00h + 3Fh a C0h (CMD to write the data byte). This latches the data byte through changing the decode bits and

begins to write NVRAM data operation.

FC00h + 3Fh until D31 = 0 (not busy).

FC00h + 3Fh an E0h (CMD to read the address latched).

FC00h + 3Fh until D31 = 0 (not busy).

FC00h + 3Eh the data.

S5335 Datasheet(PDF) 113 Page - Applied Micro Circuits Corporation

S5335 Datasheet(HTML) 113 Page - Applied Micro Circuits Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL