S5335 datasheet(117/189 Pages) AMCC

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S5335 – PCI Bus Controller, 3.3V

Revision 5.01 – November 30, 2005

AMCC Confidential and Proprietary

DS1657

117

Data Sheet

MAILBOX OVERVIEW

The S5335 has eight 32-bit mailbox registers. The

mailboxes are useful for passing command and status

information between the Add-On and the PCI bus. The

PCI interface has four incoming mailboxes (Add-On to

PCI) and four outgoing mailboxes (PCI to Add-On).

The Add-On interface has four incoming mailboxes

(PCI to Add-On) and four outgoing mailboxes (Add-On

to PCI). The PCI incoming and Add-On outgoing mail-

boxes are the same, internally. The Add-On incoming

and PCI outgoing mailboxes are also the same,

internally.

The mailbox status may be monitored in two ways.

The PCI and Add-On interfaces each have a mailbox

status register to indicate the empty/full status of bytes

within the mailboxes. The mailboxes may also be con-

figured to generate interrupts to the PCI and/or Add-

On interface. One outgoing and one incoming mailbox

on each interface can be configured to generate

interrupts.

FUNCTIONAL DESCRIPTION

Figure 71 shows a block diagram of the PCI to Add-On

mailbox registers. Add-On incoming mailbox read

accesses pass through an output interlock latch. This

prevents a PCI bus write to a PCI outgoing mailbox

from corrupting data being read by the Add-On. Figure

72 shows a block diagram of the Add-On to PCI mail-

box registers. PCI incoming mailbox reads also pass

through an interlocking mechanism. This prevents an

Add-On write to an outgoing mailbox from corrupting

data being read by the PCI bus. The following sections

describe the mailbox flag functionality and the mailbox

interrupt capabilities.

Figure 71. Block Diagram - PCI to Add-On Mailbox Register

Figure 72. Block Diagram - Add-On to PCI Mailbox Register

MAILBOX

ADD-ON

BUS

"INCOMING

MAILBOX"

SELECT

OUTPUT

INTERLOCK

LATCH

OUTPUT

DRIVER

ADD-ON

BUS

MAILBOX

FULL

"O"

LOAD ENABLE

READ ENABLE

ADD-ON

RD#

SELECT#

EMPTY/FULL FF

PCI BUS

"OUTGOING MAILBOX"

SELECTED READ ENABLE

"INCOMING MAILBOX"

MAILBOX

PCI

"INCOMING

MAILBOX"

SELECT

OUTPUT

INTERLOCK

LATCH

ADD-ON

BUS

"OUTGOING

MAILBOX"

WR#

SELECT#

PCI BUS

"INCOMING MAILBOX"

DECODE OF

ADR[6:2]

BE[3:0]#

MAILBOX

FULL

"O"

PCI READ PULSE

EMPTY/FULL FF

ADD-ON WRITE PULSE

SELECTED

READ PULSE

S5335 Datasheet(PDF) 117 Page - Applied Micro Circuits Corporation

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