S5335 datasheet(119/189 Pages) AMCC

119 / 189 page

S5335 – PCI Bus Controller, 3.3V

Revision 5.01 – November 30, 2005

AMCC Confidential and Proprietary

DS1657

119

Data Sheet

Add-On Outgoing Mailbox 4, Byte 3 Access

PCI incoming mailbox 4, byte 3 (Add-On outgoing

mailbox 4, byte 3) does not function exactly like the

other mailbox bytes. When an a serial nv memory boot

device or no external boot device is used, the S5335

pins EA7:0 are redefined to provide direct external

access to Add-On outgoing mailbox 4, byte 3. EA8 is

redefined to provide a load clock which may be used

to generate a PCI interrupt. The pins are redefined as

follows:

If the S5335 is programmed to generate a PCI inter-

rupt (INTA#), on an Add-On write to outgoing mailbox

4, byte 3, a rising edge on EMBCLK generates a PCI

interrupt. The bits EMB7:0 can be read by the PCI bus

interface by reading the PCI incoming mailbox 4, byte

3. These bits are useful to indicate various conditions

which may have caused the interrupt.

When using the S5335 with a byte-wide boot device,

the capability to generate PCI interrupts with Add-On

hardware does not exist. In this configuration, PCI

incoming mailbox 4, byte 3 (Add-On incoming mailbox

4, byte 3) cannot be used to transfer data from the

Add-On - it always returns zeros when read from the

PCI bus. This mailbox byte is sacrificed to allow the

added functionality provided when a byte-wide boot

device is not used.

BUS INTERFACE

The mailboxes appear on the Add-On and PCI bus

interfaces as eight operation registers. Four are outgo-

ing mailboxes, four are incoming mailboxes. The

mailboxes may be used to generate interrupts to each

of the interfaces. The following sections describe the

Add-On and PCI bus interfaces for the mailbox

registers.

PCI Bus Interface

The mailboxes are only accessible with the S5335 as

a PCI target. The mailbox operation registers do not

support burst accesses by an initiator. A PCI initiator

attempting to burst to the mailbox registers causes the

S5335 to respond with a target disconnect with data.

PCI writes to full outgoing mailboxes overwrite data

currently in that the mailbox. PCI reads from empty

incoming mailboxes return the data that was previ-

ously contained in the mailbox. Neither of these

situations cause a target retry or abort.

PCI incoming and outgoing mailbox interrupts are

enabled in the Interrupt Control/Status Register

(INTCSR). The mailboxes can generate a PCI inter-

rupt (INTA#) under two conditions (individually

enabled). For an incoming mailbox full interrupt, INTA#

is asserted on the PCI clock rising edge after the Add-

On mailbox write completes. For an outgoing mailbox

empty interrupt, INTA# is asserted on the PCI clock

rising edge after the Add-On mailbox read completes

(the rising edge of RD#). INTA# is deasserted on the

next PCI clock rising edge after the PCI access to

clear the mailbox interrupt completes (TRDY#

deasserted).

Add-On Bus Interface

The Add-On mailbox interface behaves similar to the

PCI bus interface. Add-On writes to full outgoing mail-

boxes overwrite data currently in that mailbox. PCI

reads from empty incoming mailboxes return the data

that was previously contained in the mailbox.

Add-On incoming and outgoing mailbox interrupts are

enabled in the Add-On Interrupt Control/Status Regis-

ter (AINT). The mailboxes can generate the Add-On

IRQ# interrupt under two conditions (individually

enabled). For an incoming mailbox full interrupt, IRQ#

is asserted one PCI clock period after the PCI mailbox

write completes (TRDY# deasserted). For an outgoing

mailbox empty interrupt, IRQ# is asserted one PCI

clock period after the PCI mailbox read completes

(TRDY# deasserted). IRQ# is deasserted immediately

when the Add-On clears the mailbox interrupt.

When the S5335 is used with a serial nv memory boot

device or no external boot device, the device pins

EA8:0 are redefined. EA7:0 become EMB7:0 data

inputs and EA8 becomes EMBCLK, a load clock. This

configuration allows the Add-On to generate PCI inter-

rupts with a low-to-high transition on EMBCLK. The

PCI incoming mailbox interrupt must be enabled and

set for mailbox 4, byte3 in the PCI Interrupt Control/

Status Register (INTCSR). EMBCLK should begin

high and be pulsed low, then high to be recognized.

The rising edge of EMBCLK generates the interrupt.

The rising edge of EMBCLK also latches in the values

on EMB7:0. The S5335 interrupt logic must be cleared

(INTA# deasserted) through INTCSR before further

EMBCLK interrupts are recognized.

Signal Pin

Add-On Outgoing Mailbox

EA0/EMB0

EA1/EMB1

EA2/EMB2

EA3/EMB3

EA4/EMB4

EA5/EMB5

EA6/EMB6

EA7/EMB7

EA8/EMBCLK

Mailbox 4, bit 24

Mailbox 4, bit 25

Mailbox 4, bit 26

Mailbox 4, bit 27

Mailbox 4, bit 28

Mailbox 4, bit 29

Mailbox 4, bit 30

Mailbox 4, bit 31

Mailbox 4, byte 3 load clock

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