S5335 datasheet(115/189 Pages) AMCC

115 / 189 page

S5335 – PCI Bus Controller, 3.3V

Revision 5.01 – November 30, 2005

AMCC Confidential and Proprietary

DS1657

115

Data Sheet

nv Memory Device Timing Requirements

For serial nv memory devices, the serial clock output

frequency is the PCI clock frequency divided by 512.

This is approximately 65 KHz (with a 33 MHz PCI

clock). Any serial memory device that operates at this

frequency is compatible with the S5335.

For byte-wide accesses, the S5335 generates the

waveforms shown in Figures 50 and 51. Figure 69

shows an nv memory read operation. Figure 70 shows

an nv memory write operation. Read operations are

always the same length. Write operations, due to the

characteristics of reprogrammable nv memory

devices, may be controlled through a programming

sequence.

Figure 69. nv Memory Read Operation

Memory Device Requirements for Read Accesses

Timing

Spec.

T = 30 ns

Read cycle time

8T(max)

240 ns

Address valid to data valid

7T–10(max)

200 ns

Address valid to read active

T(max)

30 ns

Read active to data valid

6T–10(max)

170 ns

Read pulse width

6T(max)

180 ns

Data hold from read inactive

—

2 ns

Data Valid

EQ[7:0]

(INPUT)

EA[15:0]

(OUTPUT)

ERD#

(OUTPUT)

Address Valid

t35

t36

t37

t39

t38

t41

t40

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