S5335 datasheet(121/189 Pages) AMCC

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S5335 – PCI Bus Controller, 3.3V

Revision 5.01 – November 30, 2005

AMCC Confidential and Proprietary

DS1657

121

Data Sheet

Mailbox operations for the Add-On interface are functionally identical. The following sequences are suggested for

Add-On mailbox operations using status polling (interrupts disabled):

Mailbox Interrupts

Although polling status is useful, in some cases, polling requires continuous actions by the processor reading or

writing the mailbox. Mailbox interrupt capabilities are provided to avoid much of the processor overhead required

by continuously polling status bits.

The Add-On and PCI interface can each generate interrupts on an incoming mailbox condition and/or an outgoing

mailbox condition. These can be individually enabled/disabled. A specific byte in one incoming mailbox and one

outgoing mailbox is identified to generate the interrupt(s). The tasks required to setup mailbox interrupts are shown

below:

Reading an Add-On Incoming Mailbox:

1. Check Mailbox Status. Read the mailbox status register to determine if any information has been passed from the PCI interface.

AMBEF

Bits 15:0

If a bit is set, valid data is contained in the corre-

sponding mailbox byte.

2. Read Mailbox(es). Read the mailbox bytes which AMBEF indicates are full. This automatically resets the status bits in

the AMBEF and MBEF registers.

AIMBx

Bits 31:0

Mailbox data.

Writing an Add-On Outgoing Mailbox:

1. Check Mailbox Status. Read the mailbox status register to determine if information previously written to the mailbox has

been read by the PCI interface. Writes to full mailbox bytes overwrite data currently in the mailbox (if not already read

by the PCI interface). Repeat until the byte(s) to be written are empty.

AMBEF

Bits 31:16

If a bit is set, valid data is contained in the corre-

sponding mailbox byte and has not been read by

the PCI bus.

2. Write Mailbox(es). Write to the outgoing mailbox byte(s).

AOMBx

Bits 31:0

Mailbox data.

Enabling PCI mailbox interrupts:

1. Enable PCI outgoing mailbox interrupts. A specific byte within one of the outgoing mailboxes is identified to assert

INTA# when read by the Add-On interface.

INTCSR

Bit 4

Enable outgoing mailbox interrupts

INTCSR

Bits 3:2

Identify mailbox to generate interrupt

INTCSR

Bits 1:0

Identify mailbox byte to generate interrupt

2. Enable PCI incoming mailbox interrupts. A specific byte within one of the incoming mailboxes is identified to assert

INTA# when written by the Add-On interface.

INTCSR

Bit 12

Enable incoming mailbox interrupts

INTCSR

Bits 11:10

Identify mailbox to generate interrupt

INTCSR

Bits 9:8

Identify mailbox byte to generate interrupt

S5335 Datasheet(PDF) 121 Page - Applied Micro Circuits Corporation

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