S5335 datasheet(129/189 Pages) AMCC

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S5335 – PCI Bus Controller, 3.3V

Revision 5.01 – November 30, 2005

AMCC Confidential and Proprietary

DS1657

129

Data Sheet

the management scheme and finishes transferring the

data. The second case is when the S5335 is config-

ured for Add-On initiated bus mastering with transfer

counts disabled. In this situation, the FIFO manage-

ment scheme must be set to request the PCI bus

when one or more locations are full. AMREN and

AMWEN may be used to implement a specific FIFO

management scheme.

FIFO Bus Master Cycle Priority

In many applications, the FIFO is used as a PCI initia-

tor performing both PCI reads and writes. This

requires a priority scheme be implemented. What hap-

pens if the FIFO condition for initiating a PCI read and

a PCI write are both met?

Bits D12 and D8 in the Bus Master Control/Status

ority, respectively. If these bits are both set or both

clear, priority alternates, beginning with a read cycle. If

the read priority is set and the write priority is clear,

read cycles take priority. If the write priority is set and

the read priority is clear, write cycles take priority. Pri-

ority arbitration is only done when neither FIFO has

control of the PCI bus (the PCI to Add-On FIFO would

never interrupt an Add-On to PCI FIFO transfer).

FIFO Generated Bus Master Interrupts

Interrupts may be generated under certain conditions

from the FIFO. If PCI initiated bus mastering is used,

INTA# is generated to the PCI interface. If Add-On ini-

tiated bus mastering is used, IRQ# is generated to the

Add-On interface. Interrupts may be disabled.

FIFO Interrupts may be generated from one or more of

the following during bus mastering: read transfer count

reaches zero, write transfer count reaches zero, or an

error occurs during bus mastering. Error conditions

include a target or master abort on the PCI bus. Inter-

rupts on PCI error conditions are only enabled if one or

both of the transfer count interrupts are enabled.

The Add-On Interrupt Control/Status Register (AINT)

or the Interrupt Control Status Register (INTCSR) indi-

cates the interrupt source. The interrupt service

routine may read these registers to determine what

action is required. As mailboxes are also capable of

generating interrupts, this must also be considered in

the service routine. Interrupts are also cleared through

these registers.

BUS INTERFACE

The S5335 FIFO may be accessed from the Add-On

interface or the PCI interface. Add-On FIFO control

and status signals allow a simple interface to the FIFO

with either an Add-On CPU or programmable logic.

The following section describes the PCI and Add-On

interface behavior and hardware interface.

FIFO PCI Interface (Target Mode)

The S5335 FIFO may act as a standard PCI target.

FIFO empty/full status may be determined by the PCI

initiator by reading the status bits in the PCI Bus Mas-

ter Control/Status Register (MCSR).

The FIFO occupies a single 32-bit register location

within the PCI Operation Registers. A PCI initiator

may not perform burst accesses to a FIFO as it is a

single address.

Each data phase of a burst causes

the PCI initiator to increment its address counter (even

though only the first address is driven at the beginning

of the burst). The initiator keeps track of the current

address in case a disconnect occurs. This allows the

initiator to continue the burst from where the discon-

nect occurred. If the S5335 FIFO initiated a disconnect

during a PCI burst to the FIFO register, the burst would

be resumed at an address other than the FIFO loca-

tion (because the initiator address counter has

incremented). The S5335 always signals a disconnect

if a burst to any PCI Operation Register is attempted.

Because the PCI to Add-On FIFO and the Add-On to

PCI FIFO occupy a single location within the PCI and

Add-On Operation Registers, which FIFO is accessed

is determined by whether the access is a read or write.

This means that once data is written into the FIFO, the

value written cannot be read back.

For PCI reads from the Add-On to PCI FIFO, the

S5335 asserts TRDY# and completes the PCI cycle

(Figure 77). If the PCI bus attempts to read an empty

FIFO, the S5335 immediately issues a disconnect with

retry (Figure 78). The Add-On to PCI FIFO status indi-

cators change one PCI clock after a PCI read.

For PCI writes to the PCI to Add-On, the S5335

asserts TRDY# and completes the PCI cycle (Figure

79). If the PCI bus attempts to write a full FIFO, the

S5335 immediately issues a disconnect with retry (Fig-

ure 80). The PCI to Add-On FIFO status indicators

change one PCI clock after a PCI write.

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