SH7616 datasheet(301/935 Pages) RENESAS

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Section 7 Bus State Controller (BSC)

Rev. 2.00 Mar 09, 2006 page 275 of 906

REJ09B0292-0200

A15

BA1

A14

BA0

A13

A11

CKIO

CLK

CKE

CSn

RAS

CAS

RD/

D31

I/O31

I/O0

DQMUU/

WE3

DQMUU

DQMUL/

WE2

DQMUL

DQMLU/

WE1

DQMLU

DQMLL/

WE0

DQMLL

256 Mbit

(2 Mword × 32-bit × 4 Bank)

synchronous DRAM

Chip

Figure 7.4 256 Mbit Synchronous DRAM (8 Mword × 32 bit) Connection Example

Bit 6—Memory Data Size (SZ): For synchronous DRAM and DRAM space, the data bus width of

BCR2 is ignored in favor of the specification of this bit.

Bit 6: SZ

Description

Word (16 bits)

(Initial value)

Longword (32 bits)

Bit 3—Refresh Control (RFSH): This bit determines whether or not the refresh operation of

DRAM/synchronous DRAM is performed

Bit 3: RFSH

Description

No refresh

(Initial value)

1Refresh

Bit 2—Refresh Mode (RMODE): When the RFSH bit is 1, this bit selects normal refresh or self-

refresh. When the RFSH bit is 0, do not set this bit to 1. When the RFSH bit is 1, self-refresh

mode is entered immediately after the RMODE bit is set to 1. When the RFSH bit is 1 and this bit

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