SH7616 datasheet(302/935 Pages) RENESAS

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Section 7 Bus State Controller (BSC)

Rev. 2.00 Mar 09, 2006 page 276 of 906

REJ09B0292-0200

is 0, a

CAS-before-RAS refresh or auto-refresh is performed at the interval set in the 8-bit interval

timer. When a refresh request occurs during an external area access, the refresh is performed after

the access cycle is completed. When set for self-refresh, self-refresh mode is entered immediately

unless the chip is in the middle of a synchronous DRAM area access, in which case self-refresh

mode is entered when the access ends. Refresh requests from the interval timer are ignored during

self-refresh.

Bit 2: RMODE

Description

Normal refresh

(Initial value)

Self-refresh

7.2.8

Refresh Timer Control/Status Register (RTCSR)

Bit:

————————

Initial value:

00000000

R/W:

RRRRRRRR

Bit:

76543210

CMF

CMIE

CKS2

CKS1

CKS0

RRC2

RRC1

RRC0

Initial value:

00000000

R/W:

R/W

Bits 15 to 8—Reserved: These bits are always read as 0. The write value should always be 0.

Bit 7—Compare Match Flag (CMF): This status flag, which indicates that the values of RTCNT

and RTCOR match, is set/cleared under the following conditions:

Bit 7: CMF

Description

[Clearing condition]

After RTCSR is read when CMF is 1, 0 is written in CMF

[Setting condition]

RTCNT = RTCOR

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