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DS26521 Datasheet(PDF) 156 Page - Maxim Integrated Products |
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DS26521 Datasheet(HTML) 156 Page - Maxim Integrated Products |
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156 / 258 page ![]() DS26521 Single T1/E1/J1 Transceiver 156 of 258 Register Name: RIM5 Register Description: Receive Interrupt Mask Register 5 (HDLC) Register Address: 0A4h Bit # 7 6 5 4 3 2 1 0 Name — — ROVR RHOBT RPE RPS RHWMS RNES Default 0 0 0 0 0 0 0 0 Bit 5: Receive FIFO Overrun (ROVR). 0 = interrupt masked 1 = interrupt enabled Bit 4: Receive HDLC Opening Byte Event (RHOBT). 0 = interrupt masked 1 = interrupt enabled Bit 3: Receive Packet-End Event (RPE). 0 = interrupt masked 1 = interrupt enabled Bit 2: Receive Packet-Start Event (RPS). 0 = interrupt masked 1 = interrupt enabled Bit 1: Receive FIFO Above High Watermark Set Event (RHWMS). 0 = interrupt masked 1 = interrupt enabled Bit 0: Receive FIFO Not Empty Set Event (RNES). 0 = interrupt masked 1 = interrupt enabled |
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