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DS26521 Datasheet(PDF) 153 Page - Maxim Integrated Products |
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DS26521 Datasheet(HTML) 153 Page - Maxim Integrated Products |
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153 / 258 page ![]() DS26521 Single T1/E1/J1 Transceiver 153 of 258 Register Name: RIM3 (T1 Mode) Register Description: Receive Interrupt Mask Register 3 Register Address: 0A2h Bit # 7 6 5 4 3 2 1 0 Name LORCC LSPC LDNC LUPC LORCD LSPD LDND LUPD Default 0 0 0 0 0 0 0 0 Note: For E1 mode, see RIM3. Bit 7: Loss of Receive Clock Condition Clear (LORCC). 0 = interrupt masked 1 = interrupt enabled Bit 6: Spare Code Detected Condition Clear (LSPC). 0 = interrupt masked 1 = interrupt enabled Bit 5: Loop-Down Code Detected Condition Clear (LDNC). 0 = interrupt masked 1 = interrupt enabled Bit 4: Loop-Up Code Detected Condition Clear (LUPC). 0 = interrupt masked 1 = interrupt enabled Bit 3: Loss of Receive Clock Condition Detect (LORCD). 0 = interrupt masked 1 = interrupt enabled Bit 2: Spare Code Detected Condition Detect (LSPD). 0 = interrupt masked 1 = interrupt enabled Bit 1: Loop-Down Code Detected Condition Detect (LDND). 0 = interrupt masked 1 = interrupt enabled Bit 0: Loop-Up Code Detected Condition Detect (LUPD). 0 = interrupt masked 1 = interrupt enabled |
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