DS26521 datasheet(224/258 Pages) MAXIM

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DS26521 Single T1/E1/J1 Transceiver

224 of 258

Figure 10-7. T1 Receive-Side Interleave Bus Operation—FRAME Mode

FR1 CH1-32

FR0 CH1-32

FR1 CH1-32

FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32

FR0 CH1-32

FR1 CH1-32

RSER

LSB

SYSCLK

RSYNC

FRAMER 3, CHANNEL 32

MSB

LSB

FRAMER 0, CHANNEL 1

RSIG

FRAMER 3, CHANNEL 32

FRAMER 0, CHANNEL 1

MSB

LSB

FRAMER 0, CHANNEL 2

RSER

RSYNC

RSIG

RSER

RSIG

BIT DETAIL

C/AD/B

C/A D/B

FR1 CH1-32

FR0 CH1-32

FR1 CH1-32

FR0 CH1-32

FR1 CH1-32

FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32

NOTE 1: 4.096MHz BUS CONFIGURATION.

NOTE 2: 8.192MHz BUS CONFIGURATION.

NOTE 3: RSYNC IS IN THE INPUT MODE (RIOCR.2 = 0).

NOTE 4: SHOWS SYSTEM IMPLEMENTATION WITH MULTIPLE DS26521 CORES DRIVING BACKPLANE.

NOTE 5: THOUGH NOT SHOWN, RCHCLK CONTINUES TO MARK THE CHANNEL LSB FOR THE FRAMER'S ACTIVE PERIOD.

NOTE 6: THOUGH NOT SHOWN, RCHBLK CONTINUES TO MARK THE BLOCKED CHANNELS FOR THE FRAMER’S ACTIVE PERIOD.

DS26521 Datasheet(PDF) 224 Page - Maxim Integrated Products

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