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DS26521 Datasheet(PDF) 228 Page - Maxim Integrated Products |
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DS26521 Datasheet(HTML) 228 Page - Maxim Integrated Products |
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228 / 258 page ![]() DS26521 Single T1/E1/J1 Transceiver 228 of 258 Figure 10-13. T1 Transmit-Side Interleave Bus Operation—BYTE Mode TSER LSB SYSCLK TSYNC FRAMER 3, CHANNEL 32 MSB LSB FRAMER 0, CHANNEL 1 TSIG FRAMER 3, CHANNEL 32 FRAMER 0, CHANNEL 1 MSB LSB FRAMER 1, CHANNEL 1 FRAMER 1, CHANNEL 1 3 TSER TSYNC TSIG TSER TSIG F R2 CH32 FR3 CH32 FR0 CH1 FR1 CH1 FR2 CH1 FR3 CH1 FR0 CH2 FR1 CH2 FR2 CH2 FR3 CH2 1 1 2 2 BIT DETAIL FR1 CH 32 FR 0 CH1 FR1 C H1 FR0 CH2 FR1 CH 2 FR1 CH 32 FR 0 CH1 FR1 C H1 FR0 CH2 FR1 CH 2 F R2 CH32 FR3 CH32 FR0 CH1 FR1 CH1 FR2 CH1 FR3 CH1 FR0 CH2 FR1 CH2 FR2 CH2 FR3 CH2 AB C/A D/B AB C/A D/B AB C/A D/B NOTE 1: 4.096MHz BUS CONFIGURATION. NOTE 2: 8.192MHz BUS CONFIGURATION. NOTE 3: TSYNC IS IN THE INPUT MODE (TIOCR.2 = 0). NOTE 4. THOUGH NOT SHOWN, TCHCLK CONTINUES TO MARK THE CHANNEL LSB FOR THE FRAMER'S ACTIVE PERIOD. NOTE 5: THOUGH NOT SHOWN, TCHBLK CONTINUES TO MARK THE BLOCKED CHANNELS FOR THE FRAMER’S ACTIVE PERIOD. |
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