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DS26521 Datasheet(PDF) 231 Page - Maxim Integrated Products |
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DS26521 Datasheet(HTML) 231 Page - Maxim Integrated Products |
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231 / 258 page ![]() DS26521 Single T1/E1/J1 Transceiver 231 of 258 Figure 10-17. E1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled) Figure 10-18. E1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled) RSER CHANNEL 23/31 CHANNEL 24/32 CHANNEL 1/2 RCHCLK RCHBLK RSYSCLK RSYNC 2 3 RSYNC 1 RMSYNC LSB F MSB MSB LSB 4 NOTE 1: DATA FROM THE E1 CHANNELS 1, 5, 9, 13, 17, 21, 25, AND 29 IS DROPPED (CHANNEL 2 FROM THE E1 LINK IS MAPPED TO CHANNEL 1 OF THE T1 LINK, ETC.) AND THE F-BIT POSITION IS ADDED (FORCED TO ONE). NOTE 2: RSYNC IN THE OUTPUT MODE (RIOCR.2 = 0). NOTE 3: RSYNC IN THE INPUT MODE (RIOCR.2 = 1). NOTE 4: RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 24. RSER CHANNEL 1 RCHCLK RCHBLK RSYSCLK RSYNC CHANNEL 31 CHANNEL 32 1 3 RSYNC 2 RMSYNC RSIG CHANNEL 31 CHANNEL 32 C D AB CHANNEL 1 LSB MSB LSB MSB C D B A Note 4 NOTE 1: RSYNC IN THE OUTPUT MODE (RIOCR.2 = 0). NOTE 2: RSYNC IN THE INPUT MODE (RIOCR.2 = 1). NOTE 3: RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 1. NOTE 4: RSIG NORMALLY CONTAINS THE CAS MULTIFRAME ALIGNMENT NIBBLE (0000) IN CHANNEL 1. |
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