XRT72L13 datasheet(146/370 Pages) EXAR

146 / 370 page

XRT72L13

MULTIPLEXER/FRAMER IC

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PRELIMINARY

REV. 1.0.6

134

ed by the Receive DS3 Framer block (within the chip),

since the last read of these registers. This register

contains the LSB (or Lower-Byte) value of this 16 bit

expression.

2.3.2.66 PMON P-Bit Error Event Count Regis-

ter - MSB

This "Reset-upon-Read" register, along with the

"PMON P-Bit Error Count Register - LSB" (Address =

0x55) contains a 16-bit representation of the number

of "P-bit Errors that have been detected by the Re-

ceive DS3 Framer block (within the chip), since the

last read of these registers. This register contains the

MSB (or Upper-Byte) value of this 16 bit expression.

2.3.2.67 PMON P-Bit Error Event Count Regis-

ter - LSB

This "Reset-upon-Read" register, along with the

"PMON P-Bit Error Count Register - MSB" (Address =

0x54) contains a 16-bit representation of the number

of "P-bit Errors that have been detected by the Re-

ceive DS3 Framer block (within the chip), since the

last read of these registers. This register contains the

LSB (or Lower-Byte) value of this 16 bit expression.

2.3.2.68 PMON FEBE Event Count Register -

MSB

This "Reset-upon-Read" register, along with the

"PMON FEBE Event Count Register - LSB" (Address

= 0x57) contains a 16-bit representation of the num-

ber of "FEBE Events that have been detected by the

Receive DS3 Framer block (within the chip), since the

last read of these registers. This register contains the

MSB (or Upper-Byte) value of this 16 bit expression.

2.3.2.69 PMON FEBE Event Count Register -

LSB

This "Reset-upon-Read" register, along with the

"PMON FEBE Event Count Register - MSB" (Address

= 0x56) contains a 16-bit representation of the num-

ber of "FEBE Events that have been detected by the

Receive DS3 Framer block (within the chip), since the

PMON P-BIT ERROR COUNT REGISTER - MSB (ADDRESS = 0X54)

BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0

P-Bit Error Count - High Byte

RURRUR

RUR

RURRUR

000

PMON P-BIT ERROR COUNT REGISTER - LSB (ADDRESS = 0X55)

BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0

P-Bit Error Count - Low Byte

RURRUR

RUR

RURRUR

000

PMON FEBE EVENT COUNT REGISTER - MSB (ADDRESS = 0X56)

BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0

FEBE Event Count - High Byte

RURRUR

RUR

RURRUR

000

PMON FEBE EVENT COUNT REGISTER - LSB (ADDRESS = 0X57)

BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0

FEBE Event Count - Low Byte

RURRUR

RUR

RURRUR

000

XRT72L13 Datasheet(PDF) 146 Page - Exar Corporation

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