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DP8344 Datasheet(PDF) 146 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # DP8344
Description  Biphase Communications Processor?좦CP
PDF  184 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

DP8344 Datasheet(HTML) 146 Page - National Semiconductor (TI)

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60 Reference Section (Continued)
MOVE
Move Data Memory
Syntax
MOVE
mIr
Rd
indexed register
MOVE
IraA
Rd
register-relative register
MOVE
IZan
rd
immediate-relative limited register
Affected Flags
None
Description
Moves a data memory byte into the destination register
specified The data memory source operand may specify
any one of the index register modes mIr
IraA
IZan
The index register-relative mode
IraA
forms its data
memory address by adding the contents of the index regis-
ter Ir to the unsigned 8-bit value contained in the currently
active accumulator The immediate-relative mode
IZan
forms its data memory address by adding the contents of
the index register IZ to the unsigned 8-bit immediate value
n The destination register operand Rd may specify any ac-
tive CPU register where as the destination register operand
rd is limited to the active registers R0 – R15
Example
The first example loads the current accumulator by ‘‘pop-
ping’’ an external data stack which is pointed to by the
index register IX
MOVE
a
IX
A
pop accum from ext stack
The second example demonstrates the random access of a
data byte within a logical record contained in memory The
index register IY contains the base address of the logical
record
ADDA
R9 A
calculate offset into record
MOVE
IYaA
R20
get data byte from record
In the final example the 4th element of an Error Count table
is transmitted to a host The index register IZ points to the
1st entry of the table
EXX
01
select main A alt B
MOVE
IZa3
RTR
transmit 4th element
Instruction Format
MOVE
mIr
Rd
TLF9336 – 9
MOVE
IraA
Rd
110001000
Opcode
Ir
Rd
15
6
v
40
00IW
01IX
10IY
11IZ
MOVE
IZan
rd
1001
Opcode
n
rd
15
11
3
0
T-states
3 4TR e 0
4 4TR e 1
Bus Timing
Figure 6-5 4TR e 0
Figure 6-6 4TR e 1
Operation
MOVE
mIr
Rd
data memory
xRd
MOVE
IraA
Rd
data memory
xRd
MOVE
IZan
rd
data memory
xrd
146



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