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BT8376EPF Datasheet(PDF) 262 Page - Synaptics Incorporated. |
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BT8376EPF Datasheet(HTML) 262 Page - Synaptics Incorporated. |
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262 / 323 page  Table 3-39. System Bus Registers (1 of 2) ADDR (hex) Register Label Read Write Bit Number 7 6 5 4 3 2 1 0 0D0 SBI_CR R/W X2CLK SBI_OE EMF EMBED SBI[3] SBI[2] SBI[1] SBI[0] 0D1 RSB_CR R/W BUS_RSB SIG_OFF RPCM_NEG RSYN_NEG BUS_FRZ RSB_CTR RSBI[1] RSBI[0] 0D2 RSYNC_BIT R/W ——— —— OFFSET[2] OFFSET[1] OFFSET[0] 0D3 RSYNC_TS R/W — OFFSET[9] OFFSET[8] OFFSET[7] OFFSET[6] OFFSET[5] OFFSET[4] OFFSET[3] 0D4 TSB_CR R/W BUS_TSB TX_ALIGN TPCM_NEG TSYN_NEG TSB_ALIGN TSB_CTR TSBI[1] TSBI[0] 0D5 TSYNC_BIT R/W ——— —— OFFSET[2] OFFSET[1] OFFSET[0] 0D6 TSYNC_TS R/W — OFFSET[9] OFFSET[8] OFFSET[7] OFFSET[6] OFFSET[5] OFFSET[4] OFFSET[3] 0D7 RSIG_CR R/W — SET_RSIG SET_SIG UNICODE DEBOUNCE FRZ_OFF FRZ_ON THRU 0D8 RSYNC_FRM R/W ——— OFFSET[14] OFFSET[13] OFFSET[12] OFFSET[11] OFFSET[10] 0D9 SSTAT R TSDIR TFSLIP TUSLIP — RSDIR RFSLIP RUSLIP — 0DA STACK R WORD MORE — CH[4] CH[3] CH[2] CH[1] CH[0] WORD MORE —— SIG_BITA SIG_BITB SIG_BITC SIG_BITD 0DB RPHASE R RDELAY[5] RDELAY[4] RDELAY[3] RDELAY[2] RDELAY[1] RDELAY[0] RSLIP_WR RSLIP_RD 0DC TPHASE R TDELAY[5] TDELAY[4] TDELAY[3] TDELAY[2] TDELAY[1] TDELAY[0] TSLIP_WR TSLIP_RD 0DD PERR R ——— —— PERR_TPC PERR_RPC PERR_SBC 0E0–0FF SBCn; n = 0 to 31 R/W — INSERT SIG_LP RLOOP RINDO TINDO TSIG_AB ASSIGN 100–11F TPCn; n = 0 to 31 R/W TB7ZS/EMFBIT TLOOP TIDLE TLOCAL TSIGA/TSIGO TSIGB/RSIGO TSIGC TSIGD 120–13F TSIGn; n = 00 to 31 R/W ——— — TSIGn[3] TSIGn[2] TSIGn[1] TSIGn[0] |
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